Added unwrapper testbench

stitch_project/stitch/TestbenchUnwrapper.vhd

+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   16:36:51 11/21/2024
+-- Design Name:   
+-- Module Name:   /home/ise/xilinx_vm/stitch/stitch_project/stitch/TestbenchUnwrapper.vhd
+-- Project Name:  stitch
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: DistanceUnwrapper
+-- 
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ 
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+ 
+ENTITY TestbenchUnwrapper IS
+END TestbenchUnwrapper;
+ 
+ARCHITECTURE behavior OF TestbenchUnwrapper IS 
+ 
+    -- Component Declaration for the Unit Under Test (UUT)
+ 
+    COMPONENT DistanceUnwrapper
+    PORT(
+         clk100 : IN  std_logic;
+         en : IN  std_logic;
+         dr : IN  std_logic;
+         distance_in : IN  std_logic_vector(20 downto 0);
+         distance_out : OUT  std_logic_vector(24 downto 0);
+         dr_out : OUT  std_logic
+        );
+    END COMPONENT;
+    
+
+   --Inputs
+   signal clk100 : std_logic := '0';
+   signal en : std_logic := '0';
+   signal dr : std_logic := '0';
+   signal distance_in : std_logic_vector(20 downto 0) := (others => '0');
+
+ 	--Outputs
+   signal distance_out : std_logic_vector(24 downto 0);
+   signal dr_out : std_logic;
+
+   -- Clock period definitions
+   constant clk100_period : time := 10 ns;
+BEGIN
+ 
+	-- Instantiate the Unit Under Test (UUT)
+   uut: DistanceUnwrapper PORT MAP (
+          clk100 => clk100,
+          en => en,
+          dr => dr,
+          distance_in => distance_in,
+          distance_out => distance_out,
+          dr_out => dr_out
+        );
+
+   -- Clock process definitions
+   clk100_process :process
+   begin
+		clk100 <= '0';
+		wait for clk100_period/2;
+		clk100 <= '1';
+		wait for clk100_period/2;
+   end process;
+ 
+
+   -- Stimulus process
+   stim_proc: process
+   begin		
+      -- hold reset state for 100 ns.
+      wait for 100 ns;	
+
+      wait for clk100_period*10;
+
+      -- insert stimulus here 
+		-- 0: apply desired en
+		en <= '1';
+		wait for 10ns;
+		-- 1: apply distance, dr up 
+		distance_in <= "000000000000000000000";
+		dr <= '1';
+		-- 2: wait 8 clocks
+		wait for 80ns;
+		-- 3: dr low
+		dr <= '0';
+		-- 4: wait 84 clocks
+		wait for 840ns;
+		-- 1: apply distance, dr up 
+		distance_in <= "000100000000000000000";
+		dr <= '1';
+		-- 2: wait 8 clocks
+		wait for 80ns;
+		-- 3: dr low
+		dr <= '0';
+		-- 4: wait 84 clocks
+		wait for 840ns;
+		-- 1: apply distance, dr up 
+		distance_in <= "001000000000000000000";
+		dr <= '1';
+		-- 2: wait 8 clocks
+		wait for 80ns;
+		-- 3: dr low
+		dr <= '0';
+		-- 4: wait 84 clocks
+		wait for 840ns;
+		-- 1: apply distance, dr up 
+		distance_in <= "001100000000000000000";
+		dr <= '1';
+		-- 2: wait 8 clocks
+		wait for 80ns;
+		-- 3: dr low
+		dr <= '0';
+		-- 4: wait 84 clocks
+		wait for 840ns;
+		-- 1: apply distance, dr up 
+		distance_in <= "010000000000000000000";
+		dr <= '1';
+		-- 2: wait 8 clocks
+		wait for 80ns;
+		-- 3: dr low
+		dr <= '0';
+		-- 4: wait 84 clocks
+		wait for 840ns;
+		-- 1: apply distance, dr up 
+		distance_in <= "010100000000000000000";
+		dr <= '1';
+		-- 2: wait 8 clocks
+		wait for 80ns;
+		-- 3: dr low
+		dr <= '0';
+		-- 4: wait 84 clocks
+		wait for 840ns;
+		-- 1: apply distance, dr up 
+		distance_in <= "011000000000000000000";
+		dr <= '1';
+		-- 2: wait 8 clocks
+		wait for 80ns;
+		-- 3: dr low
+		dr <= '0';
+		-- 4: wait 84 clocks
+		wait for 840ns;
+		-- 1: apply distance, dr up 
+		distance_in <= "011100000000000000000";
+		dr <= '1';
+		-- 2: wait 8 clocks
+		wait for 80ns;
+		-- 3: dr low
+		dr <= '0';
+		-- 4: wait 84 clocks
+		wait for 840ns;
+		-- 1: apply distance, dr up 
+		distance_in <= "100000000000000000000";
+		dr <= '1';
+		-- 2: wait 8 clocks
+		wait for 80ns;
+		-- 3: dr low
+		dr <= '0';
+		-- 4: wait 84 clocks
+		wait for 840ns;
+		-- 1: apply distance, dr up 
+		distance_in <= "100100000000000000000";
+		dr <= '1';
+		-- 2: wait 8 clocks
+		wait for 80ns;
+		-- 3: dr low
+		dr <= '0';
+		-- 4: wait 84 clocks
+		wait for 840ns;
+		-- 1: apply distance, dr up 
+		distance_in <= "101000000000000000000";
+		dr <= '1';
+		-- 2: wait 8 clocks
+		wait for 80ns;
+		-- 3: dr low
+		dr <= '0';
+		-- 4: wait 84 clocks
+		wait for 840ns;
+		-- 1: apply distance, dr up 
+		distance_in <= "101100000000000000000";
+		dr <= '1';
+		-- 2: wait 8 clocks
+		wait for 80ns;
+		-- 3: dr low
+		dr <= '0';
+		-- 4: wait 84 clocks
+		wait for 840ns;
+		-- 1: apply distance, dr up 
+		distance_in <= "110000000000000000000";
+		dr <= '1';
+		-- 2: wait 8 clocks
+		wait for 80ns;
+		-- 3: dr low
+		dr <= '0';
+		-- 4: wait 84 clocks
+		wait for 840ns;
+		-- 1: apply distance, dr up 
+		distance_in <= "110100000000000000000";
+		dr <= '1';
+		-- 2: wait 8 clocks
+		wait for 80ns;
+		-- 3: dr low
+		dr <= '0';
+		-- 4: wait 84 clocks
+		wait for 840ns;
+		-- 1: apply distance, dr up 
+		distance_in <= "111000000000000000000";
+		dr <= '1';
+		-- 2: wait 8 clocks
+		wait for 80ns;
+		-- 3: dr low
+		dr <= '0';
+		-- 4: wait 84 clocks
+		wait for 840ns;
+		-- 1: apply distance, dr up 
+		distance_in <= "111100000000000000000";
+		dr <= '1';
+		-- 2: wait 8 clocks
+		wait for 80ns;
+		-- 3: dr low
+		dr <= '0';
+		-- 4: wait 84 clocks
+		wait for 840ns;
+		-- 1: apply distance, dr up 
+		distance_in <= "111111111111100000000";
+		dr <= '1';
+		-- 2: wait 8 clocks
+		wait for 80ns;
+		-- 3: dr low
+		dr <= '0';
+		-- 4: wait 84 clocks
+		wait for 840ns;
+		-- 1: apply distance, dr up 
+		distance_in <= "000000001111111111111";
+		dr <= '1';
+		-- 2: wait 8 clocks
+		wait for 80ns;
+		-- 3: dr low
+		dr <= '0';
+		-- 4: wait 84 clocks
+		wait for 840ns;
+		en <= '0';
+		wait for 50ns;
+		en <= '1';
+		wait for 20ns;
+		-- 1: apply distance, dr up 
+		distance_in <= "001000001111111111111";
+		dr <= '1';
+		-- 2: wait 8 clocks
+		wait for 80ns;
+		-- 3: dr low
+		dr <= '0';
+		-- 4: wait 84 clocks
+		wait for 840ns;
+
+
+
+		
+
+      wait;
+   end process;
+
+END;

stitch_project/stitch/TestbenchUnwrapper_beh.prj

+vhdl work "DistanceUnwrapper.vhd"
+vhdl work "TestbenchUnwrapper.vhd"

stitch_project/stitch/TestbenchUnwrapper_stx_beh.prj

+vhdl isim_temp "DistanceUnwrapper.vhd"
+vhdl isim_temp "TestbenchUnwrapper.vhd"