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Commit 8d6eec69 authored by Pascal Engeler's avatar Pascal Engeler
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Changed first LED to mirror beeper

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...@@ -431,7 +431,7 @@ STX <= iSerialTransmitter_TX; ...@@ -431,7 +431,7 @@ STX <= iSerialTransmitter_TX;
DDS_OUT <= iSweeper_phi(28); DDS_OUT <= iSweeper_phi(28);
--LEDS(0) <= '1'; --LEDS(0) <= '1';
LEDS(0) <= iDistanceUnwrapper_dr_out; LEDS(0) <= Stitch_BEEPER_OUT;
LEDS(1) <= NOT iSweeper_idle; LEDS(1) <= NOT iSweeper_idle;
--LEDS(2) <= NOT iReadbackControl_idle; --LEDS(2) <= NOT iReadbackControl_idle;
or_24_23 <= iDistanceUnwrapper_distance_out(24) OR iDistanceUnwrapper_distance_out(23); or_24_23 <= iDistanceUnwrapper_distance_out(24) OR iDistanceUnwrapper_distance_out(23);
......
...@@ -8,8 +8,35 @@ ...@@ -8,8 +8,35 @@
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<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/ise/iseprojects/stitch/stitch_project/stitch/Beeper.vhd&quot; into library work</arg>
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<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/ise/iseprojects/stitch/stitch_project/stitch/CommandDecoder.vhd&quot; into library work</arg>
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<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/ise/iseprojects/stitch/stitch_project/stitch/DistanceUnwrapper.vhd&quot; into library work</arg>
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<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/ise/iseprojects/stitch/stitch_project/stitch/LaserReceiver.vhd&quot; into library work</arg>
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<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/ise/iseprojects/stitch/stitch_project/stitch/LockInAccumulator.vhd&quot; into library work</arg>
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<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/ise/iseprojects/stitch/stitch_project/stitch/ReadbackControl.vhd&quot; into library work</arg>
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<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/ise/iseprojects/stitch/stitch_project/stitch/SerialReceiver.vhd&quot; into library work</arg>
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<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/ise/iseprojects/stitch/stitch_project/stitch/SerialTransmitter.vhd&quot; into library work</arg>
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<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/ise/iseprojects/stitch/stitch_project/stitch/Stitch.vhd&quot; into library work</arg> <msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/ise/iseprojects/stitch/stitch_project/stitch/Stitch.vhd&quot; into library work</arg>
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<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/ise/iseprojects/stitch/stitch_project/stitch/Sweeper.vhd&quot; into library work</arg>
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<transform xil_pn:end_ts="1726124436" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1000327047199651568" xil_pn:start_ts="1726124436"> <transform xil_pn:end_ts="1726130533" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1000327047199651568" xil_pn:start_ts="1726130533">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1726124439" xil_pn:in_ck="-759697606739902482" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2646617551451894976" xil_pn:start_ts="1726124436"> <transform xil_pn:end_ts="1726130536" xil_pn:in_ck="-759697606739902482" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2646617551451894976" xil_pn:start_ts="1726130533">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ipcore_dir/Mem32b1024.ngc"/> <outfile xil_pn:name="ipcore_dir/Mem32b1024.ngc"/>
...@@ -161,23 +161,23 @@ ...@@ -161,23 +161,23 @@
<outfile xil_pn:name="ipcore_dir/multiaddSin.ngc"/> <outfile xil_pn:name="ipcore_dir/multiaddSin.ngc"/>
<outfile xil_pn:name="ipcore_dir/multiaddSin.vhd"/> <outfile xil_pn:name="ipcore_dir/multiaddSin.vhd"/>
</transform> </transform>
<transform xil_pn:end_ts="1726124439" xil_pn:in_ck="6231951733186561032" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1726124439"> <transform xil_pn:end_ts="1726130536" xil_pn:in_ck="6231951733186561032" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1726130536">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-7265130963783582190" xil_pn:start_ts="1726124439"> <transform xil_pn:end_ts="1726130536" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-7265130963783582190" xil_pn:start_ts="1726130536">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1726124439" xil_pn:in_ck="6231951733186561032" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1726124439"> <transform xil_pn:end_ts="1726130536" xil_pn:in_ck="6231951733186561032" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1726130536">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-3892313077777873078" xil_pn:start_ts="1726124439"> <transform xil_pn:end_ts="1726130536" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-3892313077777873078" xil_pn:start_ts="1726130536">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1726124519" xil_pn:in_ck="-2009185075857292629" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-6684372598054868263" xil_pn:start_ts="1726124439"> <transform xil_pn:end_ts="1726130616" xil_pn:in_ck="-2009185075857292629" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-6684372598054868263" xil_pn:start_ts="1726130536">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -198,11 +198,11 @@ ...@@ -198,11 +198,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/> <outfile xil_pn:name="xst"/>
</transform> </transform>
<transform xil_pn:end_ts="1726124519" xil_pn:in_ck="5505092852261115" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3812858228316398073" xil_pn:start_ts="1726124519"> <transform xil_pn:end_ts="1726130616" xil_pn:in_ck="5505092852261115" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3812858228316398073" xil_pn:start_ts="1726130616">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1726124539" xil_pn:in_ck="3802728747819461154" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="230146358404850379" xil_pn:start_ts="1726124519"> <transform xil_pn:end_ts="1726130636" xil_pn:in_ck="3802728747819461154" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="230146358404850379" xil_pn:start_ts="1726130616">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Stitch.bld"/> <outfile xil_pn:name="Stitch.bld"/>
...@@ -211,7 +211,7 @@ ...@@ -211,7 +211,7 @@
<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1726124653" xil_pn:in_ck="-3282794330040821884" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-398923363910175968" xil_pn:start_ts="1726124539"> <transform xil_pn:end_ts="1726130747" xil_pn:in_ck="-3282794330040821884" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-398923363910175968" xil_pn:start_ts="1726130636">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -225,7 +225,7 @@ ...@@ -225,7 +225,7 @@
<outfile xil_pn:name="Stitch_usage.xml"/> <outfile xil_pn:name="Stitch_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1726124766" xil_pn:in_ck="-8255871056631862401" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1726124653"> <transform xil_pn:end_ts="1726130851" xil_pn:in_ck="-8255871056631862401" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1726130747">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Stitch.ncd"/> <outfile xil_pn:name="Stitch.ncd"/>
...@@ -239,7 +239,7 @@ ...@@ -239,7 +239,7 @@
<outfile xil_pn:name="Stitch_par.xrpt"/> <outfile xil_pn:name="Stitch_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1726124805" xil_pn:in_ck="6552744863914881674" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="4970201210546912173" xil_pn:start_ts="1726124766"> <transform xil_pn:end_ts="1726130890" xil_pn:in_ck="6552744863914881674" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="4970201210546912173" xil_pn:start_ts="1726130851">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -252,7 +252,7 @@ ...@@ -252,7 +252,7 @@
<outfile xil_pn:name="webtalk.log"/> <outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1726124766" xil_pn:in_ck="3901311056773105669" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1726124741"> <transform xil_pn:end_ts="1726130851" xil_pn:in_ck="3901311056773105669" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1726130827">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Stitch.twr"/> <outfile xil_pn:name="Stitch.twr"/>
......
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