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Commit 7989aa4c authored by Pascal Engeler's avatar Pascal Engeler
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Generated bitstream

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stitch_project/stitch/Stitch.bin
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stitch_project/stitch/ipcore_dir/Mem32b1024.gise
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......@@ -32,19 +32,19 @@
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......
stitch_project/stitch/ipcore_dir/MemNsamp.gise
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− 4
View file @ 7989aa4c
......@@ -32,19 +32,19 @@
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......
stitch_project/stitch/ipcore_dir/MemSinCos.gise
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View file @ 7989aa4c
......@@ -32,19 +32,19 @@
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......
stitch_project/stitch/ipcore_dir/_xmsgs/cg.xmsgs
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......@@ -8,20 +8,5 @@
<msg type="info" file="sim" num="172" delta="old" >Generating IP...
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;multiaddCos&apos; already exists in the project. Output products for this core may be overwritten.</arg>
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;multiaddCos&apos; already exists in the project. Output products for this core may be overwritten.</arg>
</msg>
<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for &apos;multiaddCos&apos;...</arg>
</msg>
<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
</msg>
<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
</msg>
</messages>
stitch_project/stitch/ipcore_dir/cordic.gise
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......@@ -32,19 +32,19 @@
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......
stitch_project/stitch/ipcore_dir/coregen.log
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− 66
View file @ 7989aa4c
INFO:sim:172 - Generating IP...
Applying current project options...
Finished applying current project options.
WARNING:sim - A core named 'multiaddCos' already exists in the project. Output
products for this core may be overwritten.
Resolving generics for 'multiaddCos'...
WARNING:sim - A core named 'multiaddCos' already exists in the project. Output
products for this core may be overwritten.
Applying external generics to 'multiaddCos'...
Delivering associated files for 'multiaddCos'...
Generating implementation netlist for 'multiaddCos'...
INFO:sim - Pre-processing HDL files for 'multiaddCos'...
Running synthesis for 'multiaddCos'
Running ngcbuild...
Writing VHO instantiation template for 'multiaddCos'...
Writing VHDL behavioral simulation model for 'multiaddCos'...
Delivered 3 files into directory
/home/ise/iseprojects/stitch/stitch_project/stitch/ipcore_dir/tmp/_cg/multiaddCo
s
Generating ASY schematic symbol...
INFO:sim:949 - Finished generation of ASY schematic symbol.
Generating SYM schematic symbol for 'multiaddCos'...
Generating metadata file...
Generating ISE project...
XCO file found: multiaddCos.xco
XMDF file found: multiaddCos_xmdf.tcl
Adding
/home/ise/iseprojects/stitch/stitch_project/stitch/ipcore_dir/tmp/_cg/core_resou
rces.txt -view all -origin_type imported
Adding
/home/ise/iseprojects/stitch/stitch_project/stitch/ipcore_dir/tmp/_cg/gui_latenc
y.txt -view all -origin_type imported
Adding
/home/ise/iseprojects/stitch/stitch_project/stitch/ipcore_dir/tmp/_cg/multiaddCo
s.asy -view all -origin_type imported
Adding
/home/ise/iseprojects/stitch/stitch_project/stitch/ipcore_dir/tmp/_cg/multiaddCo
s.ngc -view all -origin_type created
Checking file
"/home/ise/iseprojects/stitch/stitch_project/stitch/ipcore_dir/tmp/_cg/multiaddC
os.ngc" for project device match ...
File
"/home/ise/iseprojects/stitch/stitch_project/stitch/ipcore_dir/tmp/_cg/multiaddC
os.ngc" device information matches project device.
Adding
/home/ise/iseprojects/stitch/stitch_project/stitch/ipcore_dir/tmp/_cg/multiaddCo
s.sym -view all -origin_type imported
Adding
/home/ise/iseprojects/stitch/stitch_project/stitch/ipcore_dir/tmp/_cg/multiaddCo
s.vhd -view all -origin_type created
INFO:HDLCompiler:1061 - Parsing VHDL file
"/home/ise/iseprojects/stitch/stitch_project/stitch/ipcore_dir/tmp/_cg/multia
ddCos.vhd" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/ise/iseprojects/stitch/stitch_project/stitch/ipcore_dir/tmp/_cg/multiaddCo
s.vho -view all -origin_type imported
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
Please set the new top explicitly by running the "project set top" command.
To re-calculate the new top automatically, set the "Auto Implementation Top"
property to true.
Top level has been set to "/multiaddCos"
Generating README file...
Generating FLIST file...
INFO:sim:948 - Finished FLIST file generation.
Launching README viewer...
Moving files to output directory...
Finished moving files to output directory
Wrote CGP file for project 'multiaddCos'.
Cancelled executing Tcl generator.
Wrote CGP file for project 'cordic'.
stitch_project/stitch/ipcore_dir/multiaddCos.gise
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− 4
View file @ 7989aa4c
......@@ -34,19 +34,19 @@
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......
stitch_project/stitch/ipcore_dir/multiaddSin.gise
+ 4
− 4
View file @ 7989aa4c
......@@ -34,19 +34,19 @@
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......
stitch_project/stitch/iseconfig/stitch.projectmgr
+ 22
− 17
View file @ 7989aa4c
......@@ -9,13 +9,13 @@
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</ClosedNodes>
<SelectedItems>
<SelectedItem>cordic (/home/ise/iseprojects/stitch/stitch_project/stitch/ipcore_dir/cordic.xco)</SelectedItem>
<SelectedItem>Stitch - Behavioral (/home/ise/iseprojects/stitch/stitch_project/stitch/Stitch.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
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<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>cordic (/home/ise/iseprojects/stitch/stitch_project/stitch/ipcore_dir/cordic.xco)</CurrentItem>
<CurrentItem>Stitch - Behavioral (/home/ise/iseprojects/stitch/stitch_project/stitch/Stitch.vhd)</CurrentItem>
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......@@ -23,24 +23,26 @@
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
<SelectedItem>Design Utilities</SelectedItem>
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<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
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<ItemView guiview="File" >
<ClosedNodes>
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<SelectedItems/>
<SelectedItems>
<SelectedItem>LaserReceiver.vhd</SelectedItem>
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>CommandDecoder.vhd</CurrentItem>
<CurrentItem>LaserReceiver.vhd</CurrentItem>
</ItemView>
<ItemView guiview="Library" >
<ClosedNodes>
......@@ -50,7 +52,7 @@
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem>
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......@@ -61,18 +63,21 @@
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design</ClosedNode>
<ClosedNode>Synthesize - XST</ClosedNode>
<ClosedNode>Implement Design/Map/Generate Post-Map Static Timing</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Back-annotate Pin Locations</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Generate IBIS Model</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Generate Post-Place &amp; Route Static Timing</ClosedNode>
<ClosedNode>Implement Design/Translate</ClosedNode>
<ClosedNode>User Constraints</ClosedNode>
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<CurrentItem>Design Utilities</CurrentItem>
<CurrentItem></CurrentItem>
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<ItemView engineview="SynthesisOnly" sourcetype="DESUT_XCO" guiview="Process" >
<ClosedNodes>
......@@ -84,7 +89,7 @@
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......
stitch_project/stitch/stitch.gise
+ 14
− 14
View file @ 7989aa4c
......@@ -137,15 +137,15 @@
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<transform xil_pn:end_ts="1719652324" xil_pn:in_ck="-759697606739902482" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2646617551451894976" xil_pn:start_ts="1719652323">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ipcore_dir/Mem32b1024.ngc"/>
......@@ -161,23 +161,23 @@
<outfile xil_pn:name="ipcore_dir/multiaddSin.ngc"/>
<outfile xil_pn:name="ipcore_dir/multiaddSin.vhd"/>
</transform>
<transform xil_pn:end_ts="1719629717" xil_pn:in_ck="6231951733186561032" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719629717">
<transform xil_pn:end_ts="1719652324" xil_pn:in_ck="6231951733186561032" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719652324">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719629717" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-7265130963783582190" xil_pn:start_ts="1719629717">
<transform xil_pn:end_ts="1719652324" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-7265130963783582190" xil_pn:start_ts="1719652324">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719629717" xil_pn:in_ck="6231951733186561032" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1719629717">
<transform xil_pn:end_ts="1719652324" xil_pn:in_ck="6231951733186561032" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1719652324">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719629717" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-3892313077777873078" xil_pn:start_ts="1719629717">
<transform xil_pn:end_ts="1719652324" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-3892313077777873078" xil_pn:start_ts="1719652324">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719650493" xil_pn:in_ck="5188678245468887340" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-6684372598054868263" xil_pn:start_ts="1719650483">
<transform xil_pn:end_ts="1719652332" xil_pn:in_ck="5188678245468887340" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-6684372598054868263" xil_pn:start_ts="1719652324">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -195,11 +195,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1719629727" xil_pn:in_ck="5505092852261115" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3812858228316398073" xil_pn:start_ts="1719629727">
<transform xil_pn:end_ts="1719652332" xil_pn:in_ck="5505092852261115" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3812858228316398073" xil_pn:start_ts="1719652332">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719650496" xil_pn:in_ck="-9033868516707283598" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="230146358404850379" xil_pn:start_ts="1719650493">
<transform xil_pn:end_ts="1719652335" xil_pn:in_ck="-9033868516707283598" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="230146358404850379" xil_pn:start_ts="1719652332">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Stitch.bld"/>
......@@ -208,7 +208,7 @@
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1719650514" xil_pn:in_ck="-4325218870543059951" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-398923363910175968" xil_pn:start_ts="1719650496">
<transform xil_pn:end_ts="1719652351" xil_pn:in_ck="-4325218870543059951" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-398923363910175968" xil_pn:start_ts="1719652335">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -222,7 +222,7 @@
<outfile xil_pn:name="Stitch_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1719650531" xil_pn:in_ck="-6627939747938971286" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1719650514">
<transform xil_pn:end_ts="1719652368" xil_pn:in_ck="-6627939747938971286" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1719652351">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Stitch.ncd"/>
......@@ -236,7 +236,7 @@
<outfile xil_pn:name="Stitch_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1719650538" xil_pn:in_ck="4019925351390994" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="4970201210546912173" xil_pn:start_ts="1719650531">
<transform xil_pn:end_ts="1719652375" xil_pn:in_ck="4019925351390994" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="4970201210546912173" xil_pn:start_ts="1719652368">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -249,7 +249,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1719650531" xil_pn:in_ck="-4527387296597967219" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1719650527">
<transform xil_pn:end_ts="1719652368" xil_pn:in_ck="-4527387296597967219" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1719652364">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Stitch.twr"/>
......
stitch_project/stitch/xst/work/work.vdbl
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stitch_project/stitch/xst/work/work.vdbx
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