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Commit 5e2abeab authored by Pascal Engeler's avatar Pascal Engeler
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1 merge request!2Resolve "Distance wrapping invalidates lock sum"
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stitch_project/stitch/_xmsgs/pn_parser.xmsgs
+ 1
− 25
View file @ 5e2abeab
......@@ -8,31 +8,7 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/ise/iseprojects/stitch/stitch_project/stitch/Beeper.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/ise/iseprojects/stitch/stitch_project/stitch/CommandDecoder.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/ise/iseprojects/stitch/stitch_project/stitch/LaserReceiver.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/ise/iseprojects/stitch/stitch_project/stitch/LockInAccumulator.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/ise/iseprojects/stitch/stitch_project/stitch/ReadbackControl.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/ise/iseprojects/stitch/stitch_project/stitch/SerialReceiver.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/ise/iseprojects/stitch/stitch_project/stitch/SerialTransmitter.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/ise/iseprojects/stitch/stitch_project/stitch/Stitch.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/ise/iseprojects/stitch/stitch_project/stitch/Sweeper.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/ise/iseprojects/stitch/stitch_project/stitch/DistanceUnwrapper.vhd&quot; into library work</arg>
</msg>
</messages>
......
stitch_project/stitch/ipcore_dir/Mem32b1024.gise
+ 4
− 4
View file @ 5e2abeab
......@@ -32,19 +32,19 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719654154" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3185129189393661258" xil_pn:start_ts="1719654154">
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3185129189393661258" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719654154" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7316991560476725013" xil_pn:start_ts="1719654154">
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7316991560476725013" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719654154" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719654154">
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719654154" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-4997764571106617334" xil_pn:start_ts="1719654154">
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-4997764571106617334" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
......
stitch_project/stitch/ipcore_dir/MemNsamp.gise
+ 4
− 4
View file @ 5e2abeab
......@@ -32,19 +32,19 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719654154" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-6820686459059339956" xil_pn:start_ts="1719654154">
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-6820686459059339956" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719654154" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-7915863299109585449" xil_pn:start_ts="1719654154">
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-7915863299109585449" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719654154" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719654154">
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719654154" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="5925673752377620492" xil_pn:start_ts="1719654154">
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="5925673752377620492" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
......
stitch_project/stitch/ipcore_dir/MemSinCos.gise
+ 4
− 4
View file @ 5e2abeab
......@@ -32,19 +32,19 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719654154" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-2788987222142637780" xil_pn:start_ts="1719654154">
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-2788987222142637780" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719654154" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="4978056458918207415" xil_pn:start_ts="1719654154">
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="4978056458918207415" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719654154" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719654154">
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719654154" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6045739603124474860" xil_pn:start_ts="1719654154">
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6045739603124474860" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
......
stitch_project/stitch/ipcore_dir/cordic.gise
+ 4
− 4
View file @ 5e2abeab
......@@ -32,19 +32,19 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719654154" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8782926585333300168" xil_pn:start_ts="1719654154">
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8782926585333300168" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719654154" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7818039811878659395" xil_pn:start_ts="1719654154">
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7818039811878659395" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719654154" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719654154">
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719654154" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3776669437272252152" xil_pn:start_ts="1719654154">
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3776669437272252152" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
......
stitch_project/stitch/ipcore_dir/multiaddCos.gise
+ 23
− 2
View file @ 5e2abeab
......@@ -26,9 +26,30 @@
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="gui_latency.txt" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_ASY" xil_pn:name="multiaddCos.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="multiaddCos.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="multiaddCos.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="multiaddCos.veo" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1719622862" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1719622862">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-6854975743064405440" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8175489371127869360" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="4442281788066732546" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>
stitch_project/stitch/ipcore_dir/multiaddCos.xise
+ 2
− 2
View file @ 5e2abeab
......@@ -17,11 +17,11 @@
<files>
<file xil_pn:name="multiaddCos.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="multiaddCos.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="6"/>
......
stitch_project/stitch/ipcore_dir/multiaddSin.gise
+ 23
− 2
View file @ 5e2abeab
......@@ -26,9 +26,30 @@
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="gui_latency.txt" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_ASY" xil_pn:name="multiaddSin.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="multiaddSin.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="multiaddSin.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="multiaddSin.veo" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1719622862" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1719622862">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1669001868035964362" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-3351964163447721734" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5480484674542449268" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>
stitch_project/stitch/ipcore_dir/multiaddSin.xise
+ 2
− 2
View file @ 5e2abeab
......@@ -17,11 +17,11 @@
<files>
<file xil_pn:name="multiaddSin.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="multiaddSin.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="6"/>
......
stitch_project/stitch/iseconfig/stitch.projectmgr
+ 6
− 6
View file @ 5e2abeab
......@@ -9,13 +9,13 @@
<ClosedNodesVersion>2</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Stitch - Behavioral (/home/ise/iseprojects/stitch/stitch_project/stitch/Stitch.vhd)</SelectedItem>
<SelectedItem>iLockInAccumulator - LockInAccumulator - Behavioral (/home/ise/iseprojects/stitch/stitch_project/stitch/LockInAccumulator.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000259000000020000000000000000000000000200000064ffffffff000000810000000300000002000002590000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>Stitch - Behavioral (/home/ise/iseprojects/stitch/stitch_project/stitch/Stitch.vhd)</CurrentItem>
<CurrentItem>iLockInAccumulator - LockInAccumulator - Behavioral (/home/ise/iseprojects/stitch/stitch_project/stitch/LockInAccumulator.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
<ClosedNodes>
......@@ -40,7 +40,7 @@
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000268000000040101000100000000000000000000000064ffffffff0000008100000000000000040000009400000001000000000000005d0000000100000000000000840000000100000000000000f30000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000004df000000040101000100000000000000000000000064ffffffff0000008100000000000000040000009400000001000000000000005d00000001000000000000008400000001000000000000036a0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>LaserReceiver.vhd</CurrentItem>
</ItemView>
......@@ -52,7 +52,7 @@
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000268000000010001000100000000000000000000000064ffffffff000000810000000000000001000002680000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000128000000010001000100000000000000000000000064ffffffff000000810000000000000001000001280000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem>
</ItemView>
......@@ -73,9 +73,9 @@
<SelectedItems>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >12</ScrollbarPosition>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000259000000010000000100000000000000000000000064ffffffff000000810000000000000001000002590000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000268000000010000000100000000000000000000000064ffffffff000000810000000000000001000002680000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
......
stitch_project/stitch/stitch.gise
+ 55
− 44
View file @ 5e2abeab
......@@ -128,6 +128,8 @@
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="ipcore_dir/cordic_readme.txt"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="ipcore_dir/coregen.log"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="ipcore_dir/multiaddCos.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="ipcore_dir/multiaddSin.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
......@@ -135,15 +137,15 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1719654152" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1719654152">
<transform xil_pn:end_ts="1719693565" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1719693565">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719654152" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1000327047199651568" xil_pn:start_ts="1719654152">
<transform xil_pn:end_ts="1719693565" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1000327047199651568" xil_pn:start_ts="1719693565">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719654154" xil_pn:in_ck="-759697606739902482" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2646617551451894976" xil_pn:start_ts="1719654152">
<transform xil_pn:end_ts="1719693566" xil_pn:in_ck="-759697606739902482" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2646617551451894976" xil_pn:start_ts="1719693565">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ipcore_dir/Mem32b1024.ngc"/>
......@@ -159,27 +161,26 @@
<outfile xil_pn:name="ipcore_dir/multiaddSin.ngc"/>
<outfile xil_pn:name="ipcore_dir/multiaddSin.vhd"/>
</transform>
<transform xil_pn:end_ts="1719654154" xil_pn:in_ck="6231951733186561032" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719654154">
<transform xil_pn:end_ts="1719693566" xil_pn:in_ck="6231951733186561032" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719654154" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-7265130963783582190" xil_pn:start_ts="1719654154">
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-7265130963783582190" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719654154" xil_pn:in_ck="6231951733186561032" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1719654154">
<transform xil_pn:end_ts="1719693566" xil_pn:in_ck="6231951733186561032" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719654154" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-3892313077777873078" xil_pn:start_ts="1719654154">
<transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-3892313077777873078" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719654163" xil_pn:in_ck="5188678245468887340" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-6684372598054868263" xil_pn:start_ts="1719654154">
<transform xil_pn:end_ts="1719693578" xil_pn:in_ck="-2009185075857292629" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-6684372598054868263" xil_pn:start_ts="1719693566">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="Stitch.lso"/>
......@@ -194,56 +195,66 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1719654163" xil_pn:in_ck="5505092852261115" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3812858228316398073" xil_pn:start_ts="1719654163">
<transform xil_pn:end_ts="1719693578" xil_pn:in_ck="5505092852261115" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3812858228316398073" xil_pn:start_ts="1719693578">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1719654167" xil_pn:in_ck="-9033868516707283598" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="230146358404850379" xil_pn:start_ts="1719654163">
<transform xil_pn:end_ts="1719693582" xil_pn:in_ck="-9033868516707283598" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="230146358404850379" xil_pn:start_ts="1719693578">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="Stitch.bld"/>
<outfile xil_pn:name="Stitch.ngd"/>
<outfile xil_pn:name="Stitch_ngdbuild.xrpt"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1719654184" xil_pn:in_ck="-4325218870543059951" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-398923363910175968" xil_pn:start_ts="1719654167">
<transform xil_pn:end_ts="1719693599" xil_pn:in_ck="-4325218870543059951" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-398923363910175968" xil_pn:start_ts="1719693582">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Stitch.pcf"/>
<outfile xil_pn:name="Stitch_map.map"/>
<outfile xil_pn:name="Stitch_map.mrp"/>
<outfile xil_pn:name="Stitch_map.ncd"/>
<outfile xil_pn:name="Stitch_map.ngm"/>
<outfile xil_pn:name="Stitch_map.xrpt"/>
<outfile xil_pn:name="Stitch_summary.xml"/>
<outfile xil_pn:name="Stitch_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1719654204" xil_pn:in_ck="-6627939747938971286" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1719654184">
<transform xil_pn:end_ts="1719693617" xil_pn:in_ck="-6627939747938971286" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1719693599">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Stitch.ncd"/>
<outfile xil_pn:name="Stitch.pad"/>
<outfile xil_pn:name="Stitch.par"/>
<outfile xil_pn:name="Stitch.ptwx"/>
<outfile xil_pn:name="Stitch.unroutes"/>
<outfile xil_pn:name="Stitch.xpi"/>
<outfile xil_pn:name="Stitch_pad.csv"/>
<outfile xil_pn:name="Stitch_pad.txt"/>
<outfile xil_pn:name="Stitch_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1719654210" xil_pn:in_ck="4019925351390994" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="4970201210546912173" xil_pn:start_ts="1719654204">
<transform xil_pn:end_ts="1719693624" xil_pn:in_ck="4019925351390994" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="4970201210546912173" xil_pn:start_ts="1719693617">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Stitch.bgn"/>
<outfile xil_pn:name="Stitch.bin"/>
<outfile xil_pn:name="Stitch.bit"/>
<outfile xil_pn:name="Stitch.drc"/>
<outfile xil_pn:name="Stitch.ut"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1719654204" xil_pn:in_ck="-4527387296597967219" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1719654199">
<transform xil_pn:end_ts="1719693617" xil_pn:in_ck="-4527387296597967219" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1719693613">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Stitch.twr"/>
<outfile xil_pn:name="Stitch.twx"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
</transform>
</transforms>
......
stitch_project/stitch/stitch.xise
+ 7
− 3
View file @ 5e2abeab
......@@ -25,7 +25,7 @@
</file>
<file xil_pn:name="CommandDecoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="Sweeper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
......@@ -65,7 +65,7 @@
</file>
<file xil_pn:name="Stitch.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="122"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="SerialTransmitter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="123"/>
......@@ -76,7 +76,11 @@
</file>
<file xil_pn:name="Beeper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="125"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="DistanceUnwrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="167"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="ipcore_dir/multiaddSin.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......
stitch_project/stitch/xst/work/work.vdbl
+ 0
− 0
View file @ 5e2abeab
No preview for this file type
stitch_project/stitch/xst/work/work.vdbx
+ 0
− 0
View file @ 5e2abeab
No preview for this file type
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