Added unwrapper, hooked components up correctly

stitch_project/stitch/Stitch.vhd

@@ -107,6 +107,9 @@ signal iLockInAccumulator_dataSin : STD_LOGIC_VECTOR(63 downto 0);
 signal iLockInAccumulator_n_samples : STD_LOGIC_VECTOR(31 downto 0);
 signal iLockInAccumulator_idle : STD_LOGIC;
 
+signal iDistanceUnwrapper_distance_out : STD_LOGIC_VECTOR(24 downto 0);
+signal iDistanceUnwrapper_dr_out : STD_LOGIC;
+
 signal iCordic_x_out : STD_LOGIC_VECTOR(20 DOWNTO 0);
 signal iCordic_y_out : STD_LOGIC_VECTOR(20 DOWNTO 0);
 signal iCordic_rdy : STD_LOGIC;
@@ -193,6 +196,17 @@ Port (
 );
 END COMPONENT;
 
+COMPONENT DistanceUnwrapper
+Port (
+    clk100 : in STD_LOGIC;
+    en : in STD_LOGIC;
+    dr : in STD_LOGIC;
+    distance_in : in STD_LOGIC_VECTOR(20 downto 0);
+    distance_out : out STD_LOGIC_VECTOR(24 downto 0);
+    dr_out : out STD_LOGIC
+);
+END COMPONENT;
+
 COMPONENT LockInAccumulator
 Port ( 
     CLK100 : in  STD_LOGIC;
@@ -493,8 +507,8 @@ iLockInAccumulator : LockInAccumulator port map(
 	CLK100 => Stitch_CLK100,  -- in  STD_LOGIC
 	sin => iCordic_y_out,  -- in STD_LOGIC_VECTOR(20 downto 0)
 	cos => iCordic_x_out,  -- in STD_LOGIC_VECTOR(20 downto 0)
-	data => iLaserReceiver_DISTANCE,  -- in STD_LOGIC_VECTOR(20 downto 0)
-	trig => iLaserReceiver_DATA_READY,  -- in STD_LOGIC
+	data => iDistanceUnwrapper_distance_out,  -- in STD_LOGIC_VECTOR(20 downto 0)
+	trig => iDistanceUnwrapper_dr_out,  -- in STD_LOGIC
 	clear => iSweeper_lockin_clear,  -- in STD_LOGIC
 	enable => iSweeper_lockin_en,  -- in STD_LOGIC
 	dataCos => iLockInAccumulator_dataCos,  -- out STD_LOGIC_VECTOR(63 downto 0)
@@ -503,6 +517,15 @@ iLockInAccumulator : LockInAccumulator port map(
 	idle => iLockInAccumulator_idle  -- out STD_LOGIC
 );
 
+iDistanceUnwrapper : DistanceUnwrapper port map(
+    clk100 => Stitch_CLK100,
+    en => iSweeper_lockin_en,
+    dr => iLaserReceiver_DATA_READY,
+    distance_in => iLaserReceiver_DISTANCE,
+    distance_out => iDistanceUnwrapper_distance_out,
+    dr_out => iDistanceUnwrapper_dr_out
+);
+
 --TODO: The clocking and data input and stuff may need some optimizations. Refer to the manual in ISE, esp. pertaining parallel vs word serial
 iCordic : cordic port map(
 	phase_in => phi_clean,  -- IN STD_LOGIC_VECTOR(31 DOWNTO 0)