Widened buses, input by sign extension

stitch_project/stitch/LockInAccumulator.vhd

@@ -27,7 +27,7 @@ entity LockInAccumulator is
     Port ( CLK100 : in  STD_LOGIC;
            sin : in STD_LOGIC_VECTOR(20 downto 0);
            cos : in STD_LOGIC_VECTOR(20 downto 0);
-           data : in STD_LOGIC_VECTOR(20 downto 0);
+           data : in STD_LOGIC_VECTOR(24 downto 0);
            trig : in STD_LOGIC;
            clear : in STD_LOGIC;
            enable : in STD_LOGIC;
@@ -45,9 +45,9 @@ signal current_state: STATE_T := STATE_IDLE;
 signal clear_old: STD_LOGIC := '0';
 signal trig_old: STD_LOGIC := '0';
 
-signal sinInternal : STD_LOGIC_VECTOR(20 downto 0);
-signal cosInternal : STD_LOGIC_VECTOR(20 downto 0);
-signal dataInternal : STD_LOGIC_VECTOR(20 downto 0);
+signal sinInternal : STD_LOGIC_VECTOR(24 downto 0) := (others => '0');
+signal cosInternal : STD_LOGIC_VECTOR(24 downto 0) := (others => '0');
+signal dataInternal : STD_LOGIC_VECTOR(24 downto 0) := (others => '0');
 signal trigInternal : STD_LOGIC := '0';
 signal enableInternal : STD_LOGIC := '1';
 signal clearInternal : STD_LOGIC := '0';
@@ -55,9 +55,9 @@ signal bypassInternal : STD_LOGIC := '0';
 signal n_samples_int : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
 signal idle_int: STD_LOGIC := '1';
 
-signal sinApplied : STD_LOGIC_VECTOR(20 downto 0) := (others => '0');
-signal cosApplied : STD_LOGIC_VECTOR(20 downto 0) := (others => '0');
-signal dataApplied : STD_LOGIC_VECTOR(20 downto 0) := (others => '0');
+signal sinApplied : STD_LOGIC_VECTOR(24 downto 0) := (others => '0');
+signal cosApplied : STD_LOGIC_VECTOR(24 downto 0) := (others => '0');
+signal dataApplied : STD_LOGIC_VECTOR(24 downto 0) := (others => '0');
 
 signal dataAccumSin : STD_LOGIC_VECTOR(69 downto 0);
 signal dataAccumCos : STD_LOGIC_VECTOR(69 downto 0);
@@ -69,8 +69,8 @@ PORT (
     ce : IN STD_LOGIC;
     sclr : IN STD_LOGIC;
     bypass : IN STD_LOGIC;
-    a : IN STD_LOGIC_VECTOR(20 DOWNTO 0);
-    b : IN STD_LOGIC_VECTOR(20 DOWNTO 0);
+    a : IN STD_LOGIC_VECTOR(24 DOWNTO 0);
+    b : IN STD_LOGIC_VECTOR(24 DOWNTO 0);
     s : OUT STD_LOGIC_VECTOR(69 DOWNTO 0)
   );
 END COMPONENT;
@@ -80,8 +80,8 @@ PORT (
     ce : IN STD_LOGIC;
     sclr : IN STD_LOGIC;
     bypass : IN STD_LOGIC;
-    a : IN STD_LOGIC_VECTOR(20 DOWNTO 0);
-    b : IN STD_LOGIC_VECTOR(20 DOWNTO 0);
+    a : IN STD_LOGIC_VECTOR(24 DOWNTO 0);
+    b : IN STD_LOGIC_VECTOR(24 DOWNTO 0);
     s : OUT STD_LOGIC_VECTOR(69 DOWNTO 0)
   );
 END COMPONENT;
@@ -120,8 +120,17 @@ begin
     if rising_edge(CLK100) then
         case current_state is
             when STATE_IDLE =>
-                sinInternal <= sin;
-                cosInternal <= cos;
+                --latch SIGNED sin by sign extending
+                sinInternal(20 downto 0) <= sin;
+                sinInternal(24) <= sin(20);
+                sinInternal(23) <= sin(20);
+                sinInternal(22) <= sin(20);
+                sinInternal(21) <= sin(20);
+                cosInternal(20 downto 0) <= cos;
+                cosInternal(24) <= cos(20);
+                cosInternal(23) <= cos(20);
+                cosInternal(22) <= cos(20);
+                cosInternal(21) <= cos(20);
                 dataInternal <= data;
                 sinApplied <= (others => '0');
                 cosApplied <= (others => '0');