Implemented fix for locking trace readback component (issue #13)

stitch_project/stitch/ReadbackTraceControl.vhd

@@ -10,7 +10,8 @@ entity ReadbackTraceControl is
            serial_trans_idle : in  STD_LOGIC;
            addr_rd : out  STD_LOGIC_VECTOR (14 downto 0); -- address read
            idle : out  STD_LOGIC;
-           send : out  STD_LOGIC);
+           send : out  STD_LOGIC;
+		   sel: in STD_LOGIC);
 end ReadbackTraceControl;
 
 architecture Behavioral of ReadbackTraceControl is
@@ -42,7 +43,7 @@ begin
 	if rising_edge(clk100) then
 		case current_state is
 		when IDLE_S =>
-			if start_old_sig = '0' and start = '1' then
+			if start_old_sig = '0' and start = '1' and sel = '1' then
 				current_state <= APP_ADDR;
 				idle_sig <= '0';
 			else

stitch_project/stitch/Stitch.vhd

@@ -307,7 +307,8 @@ Port (
     serial_trans_idle : in  STD_LOGIC;
     addr_rd : out  STD_LOGIC_VECTOR (14 downto 0);
     idle : out  STD_LOGIC;
-    send : out  STD_LOGIC
+    send : out  STD_LOGIC;
+    sel : in STD_LOGIC
 );
 END COMPONENT;
 
@@ -745,7 +746,8 @@ iReadbackTraceControl : ReadbackTraceControl port map(
 	serial_trans_idle => iSerialTransmitter_IDLE,  -- in  STD_LOGIC
 	addr_rd => iReadbackTraceControl_addr_rd,  -- out  STD_LOGIC_VECTOR (14 downto 0) TODO
 	idle => iReadbackTraceControl_idle,  -- out  STD_LOGIC
-	send => iReadbackTraceControl_send  -- out  STD_LOGIC
+	send => iReadbackTraceControl_send,  -- out  STD_LOGIC
+    sel => iCommandDecoder_sel
 );
 
 iMultiplexer : Multiplexer port map(