Fixed phi signal routing bug

stitch_project/stitch/Stitch.vhd

@@ -149,6 +149,8 @@ signal tx_data: STD_LOGIC_VECTOR(199 downto 0);
 
 signal sincos_concat: STD_LOGIC_VECTOR(127 downto 0);
 
+signal phi_clean: STD_LOGIC_VECTOR(31 downto 0);
+
 
 
 
@@ -414,6 +416,9 @@ LEDS(0) <= '1';
 LEDS(1) <= NOT iSweeper_idle;
 LEDS(2) <= NOT iReadbackControl_idle;
 
+phi_clean(31 downto 1) <= iSweeper_phi(30 downto 0);
+phi_clean(0) <= '0';
+
 -- instantiate components here
 
 --BUFS for LVDS in
@@ -500,7 +505,7 @@ iLockInAccumulator : LockInAccumulator port map(
 
 --TODO: The clocking and data input and stuff may need some optimizations. Refer to the manual in ISE, esp. pertaining parallel vs word serial
 iCordic : cordic port map(
-	phase_in => iSweeper_phi,  -- IN STD_LOGIC_VECTOR(31 DOWNTO 0)
+	phase_in => phi_clean,  -- IN STD_LOGIC_VECTOR(31 DOWNTO 0)
 	x_out => iCordic_x_out,  -- OUT STD_LOGIC_VECTOR(20 DOWNTO 0)
 	y_out => iCordic_y_out,  -- OUT STD_LOGIC_VECTOR(20 DOWNTO 0)
 	rdy => iCordic_rdy,  -- OUT STD_LOGIC