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Commit a1c9784c authored by Pascal Engeler's avatar Pascal Engeler
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various bugfixes

parent a225b24e
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......@@ -22,6 +22,12 @@ CMD_START = 2**3
CMD_READBACK = 2**3+2**0
CMD_RESET = 2**3+2**1
def vectToScalar(data):
cumsum = 0
for i in range(8):
cumsum = cumsum*256 + data[7-i]
return cumsum
class Stitch:
......@@ -79,18 +85,27 @@ class Stitch:
arr[0] = CMD_READBACK
self._sendArray(arr)
#now read until timeout
if not self.alwaysOpen:
self.serialHandle = serial.Serial(self.serialPort, self.baudRate, bytesize=8, stopbits=1, timeout=5)
data = self.serialHandle.read(20*self.numFreqs)
print(f"Received {len(data)/20} frames")
if not self.alwaysOpen:
self.close()
print(f"Received {int(len(data)/20)} frames")
#print(data)
cosineData = []
sineData = []
numberData = []
for i in range(self.numFreqs):
cosData = int.from_bytes(data[i*20:i*20+8], byteorder='little')
sinData = int.from_bytes(data[i*20+8:i*20+16], byteorder='little')
numData = int.from_bytes(data[i*20+16:i*20+20], byteorder='little')
cosineData.append(float(cosData)/float(numData))
sineData.append(float(sinData)/float(numData))
numberData.append(numData)
cosineData.append([data[i*20:i*20+8]])
sineData.append([data[i*20+8:i*20+16]])
numberData.append([data[i*20+16:i*20+20]])
#for i in range(self.numFreqs):
#cosData = int.from_bytes(data[i*20:i*20+8], byteorder='little')
#sinData = int.from_bytes(data[i*20+8:i*20+16], byteorder='little')
#numData = int.from_bytes(data[i*20+16:i*20+20], byteorder='little')
#cosineData.append(float(cosData)/float(numData))
#sineData.append(float(sinData)/float(numData))
#numberData.append(numData)
return numberData, cosineData, sineData
......@@ -106,25 +121,31 @@ class Stitch:
def setRegister(self, value):
arr = np.zeros(7,dtype='uint8')
#set 4:0 bits of register
arr[0] = DEST_REG_4dt0 + (value&15)
arr[0] = DEST_REG_4dt0 + (value&31)
#set 9:5 bits of register
value = value >> 4
arr[1] = DEST_REG_9dt5 + (value&15)
value = value >> 5
arr[1] = DEST_REG_9dt5 + (value&31)
#set 14:10 bits of register
value = value >> 4
arr[2] = DEST_REG_14dt10 + (value&15)
value = value >> 5
arr[2] = DEST_REG_14dt10 + (value&31)
#set 19:15 bits of register
value = value >> 4
arr[3] = DEST_REG_19dt15 + (value&15)
value = value >> 5
arr[3] = DEST_REG_19dt15 + (value&31)
#set 24:20 bits of register
value = value >> 4
arr[4] = DEST_REG_24dt20 + (value&15)
value = value >> 5
arr[4] = DEST_REG_24dt20 + (value&31)
#set 29:25 bits of register
value = value >> 4
arr[5] = DEST_REG_29dt25 + (value&15)
value = value >> 5
arr[5] = DEST_REG_29dt25 + (value&31)
#set 31:30 bits of register
value = value >> 4
arr[6] = DEST_REG_31dt30 + (value&15)
value = value >> 5
arr[6] = DEST_REG_31dt30 + (value&31)
#checkValue = 0
#for i,entry in enumerate(arr):
# checkValue += (int(entry)&31)*2**(i*5)
# print(f"Entry {i}: {entry} -> {entry&31} -> {int(entry)&31}")
#print(arr)
#print(int(checkValue))
self._sendArray(arr)
def dphiWrite(self):
......@@ -156,17 +177,6 @@ class Stitch:
arr = np.zeros(1,dtype='uint8')
arr[0] = CMD_NFREQS_MV
self._sendArray(arr)
def startExperiment(self):
arr = np.zeros(1,dtype='uint8')
arr[0] = CMD_START
self._sendArray(arr)
def getData(self):
arr = np.zeros(1,dtype='uint8')
arr[0] = CMD_READBACK
self._sendArray(arr)
#now read until timeout
def _sendArray(self, transferBuffer):
if not self.alwaysOpen:
......
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