Implemented LockInAccumulator

stitch_project/stitch/LockInAccumulator.vhd

@@ -16,4 +16,194 @@
 -- Revision 0.01 - File Created
 -- Additional Comments: 
 --
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\ No newline at end of file
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity LockInAccumulator is
+    Port ( CLK100 : in  STD_LOGIC;
+           sin : in STD_LOGIC_VECTOR(20 downto 0);
+           cos : in STD_LOGIC_VECTOR(20 downto 0);
+           data : in STD_LOGIC_VECTOR(20 downto 0);
+           trig : in STD_LOGIC;
+           clear : in STD_LOGIC;
+           enable : in STD_LOGIC;
+           dataCos : out STD_LOGIC_VECTOR(63 downto 0);
+           dataSin : out STD_LOGIC_VECTOR(63 downto 0);
+           n_samples : out STD_LOGIC_VECTOR(31 downto 0);
+           idle : out STD_LOGIC);
+end LockInAccumulator;
+
+architecture Behavioral of LockInAccumulator is
+type STATE_T is ( STATE_IDLE, STATE_tr1, STATE_tr2, STATE_tr3, STATE_cl1, STATE_cl2, STATE_cl3, STATE_cl4);
+
+--Signals here
+signal current_state: STATE_T := STATE_IDLE;
+signal clear_old: STD_LOGIC := '0';
+signal trig_old: STD_LOGIC := '0';
+
+signal sinInternal : STD_LOGIC_VECTOR(20 downto 0);
+signal cosInternal : STD_LOGIC_VECTOR(20 downto 0);
+signal dataInternal : STD_LOGIC_VECTOR(20 downto 0);
+signal trigInternal : STD_LOGIC := '0';
+signal enableInternal : STD_LOGIC := '0';
+signal clearInternal : STD_LOGIC := '0';
+signal n_samples_int : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
+signal idle_int: STD_LOGIC := '1';
+
+--Compontents here
+COMPONENT multiaddSin
+PORT (
+    clk : IN STD_LOGIC;
+    ce : IN STD_LOGIC;
+    sclr : IN STD_LOGIC;
+    a : IN STD_LOGIC_VECTOR(20 DOWNTO 0);
+    b : IN STD_LOGIC_VECTOR(20 DOWNTO 0);
+    s : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
+);
+END COMPONENT;
+COMPONENT multiaddCos
+PORT (
+    clk : IN STD_LOGIC;
+    ce : IN STD_LOGIC;
+    sclr : IN STD_LOGIC;
+    a : IN STD_LOGIC_VECTOR(20 DOWNTO 0);
+    b : IN STD_LOGIC_VECTOR(20 DOWNTO 0);
+    s : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
+);
+END COMPONENT;
+
+
+
+
+begin
+
+iMultiaddSin: multiaddSin port map(trigInternal, enableInternal, clearInternal, sinInternal, dataInternal, dataSin);
+iMultiaddCos: multiaddCos port map(trigInternal, enableInternal, clearInternal, cosInternal, dataInternal, dataCos);
+n_samples <= n_samples_int;
+idle <= idle_int;
+
+
+
+--processes here
+updateClear: process(CLK100)
+begin
+    if rising_edge(CLK100) then
+        clear_old <= clear;
+    end if;
+end process;
+
+updateTrigger: process(CLK100)
+begin
+	if rising_edge(CLK100) then
+        trig_old <= trig;
+    end if;
+end process;
+
+stateProcess: process(CLK100)
+begin
+    if rising_edge(CLK100) then
+        case current_state is
+            when STATE_IDLE =>
+                sinInternal <= sin;
+                cosInternal <= cos;
+                dataInternal <= data;
+                trigInternal <= '0';
+                enableInternal <= '1';
+                clearInternal <= '0';
+                n_samples_int <= n_samples_int;
+                idle_int <= '1';
+                if trig_old = '0' and trig = '1' and enable = '1' then
+                    --triggered
+                    current_state <= STATE_tr1;
+                elsif clear_old = '0' and clear = '1' then
+                    current_state <= STATE_cl1;
+                else
+                    current_state <= current_state;
+                end if;
+            when STATE_tr1 =>
+                --increment n_samples, trigger accumulators
+                sinInternal <= sinInternal;
+                cosInternal <= cosInternal;
+                dataInternal <= dataInternal;
+                trigInternal <= '1';
+                enableInternal <= '1';
+                clearInternal <= '0';
+                n_samples_int <= n_samples_int + 1;
+                idle_int <= '0';
+                current_state <= STATE_tr2;
+            when STATE_tr2 =>
+                --trigger down
+                sinInternal <= sinInternal;
+                cosInternal <= cosInternal;
+                dataInternal <= dataInternal;
+                trigInternal <= '0';
+                enableInternal <= '1';
+                clearInternal <= '0';
+                n_samples_int <= n_samples_int;
+                idle_int <= '0';
+                current_state <= STATE_tr3;
+            when STATE_tr3 =>
+                --buffer
+                sinInternal <= sinInternal;
+                cosInternal <= cosInternal;
+                dataInternal <= dataInternal;
+                trigInternal <= '0';
+                enableInternal <= '1';
+                clearInternal <= '0';
+                n_samples_int <= n_samples_int;
+                idle_int <= '0';
+                current_state <= STATE_IDLE;
+            when STATE_cl1 =>
+                --clear high, n_samples reset
+                sinInternal <= sinInternal;
+                cosInternal <= cosInternal;
+                dataInternal <= dataInternal;
+                trigInternal <= '0';
+                enableInternal <= '1';
+                clearInternal <= '1';
+                n_samples_int <= (others => '0');
+                idle_int <= '0';
+                current_state <= STATE_cl2;
+            when STATE_cl2 =>
+                --trigger high
+                sinInternal <= sinInternal;
+                cosInternal <= cosInternal;
+                dataInternal <= dataInternal;
+                trigInternal <= '1';
+                enableInternal <= '1';
+                clearInternal <= '1';
+                n_samples_int <= n_samples_int;
+                idle_int <= '0';
+                current_state <= STATE_cl3;
+            when STATE_cl3 =>
+                --trigger dn
+                sinInternal <= sinInternal;
+                cosInternal <= cosInternal;
+                dataInternal <= dataInternal;
+                trigInternal <= '0';
+                enableInternal <= '1';
+                clearInternal <= '1';
+                n_samples_int <= n_samples_int;
+                idle_int <= '0';
+                current_state <= STATE_cl4;
+            when STATE_cl4 =>
+                --clear dn
+                sinInternal <= sinInternal;
+                cosInternal <= cosInternal;
+                dataInternal <= dataInternal;
+                trigInternal <= '0';
+                enableInternal <= '1';
+                clearInternal <= '0';
+                n_samples_int <= n_samples_int;
+                idle_int <= '0';
+                current_state <= STATE_IDLE;
+        end case;
+    end if;
+end process;
+
+end Behavioral;
+