Lengthened delay line

stitch_project/stitch/SerialReceiver.vhd

@@ -33,7 +33,7 @@ architecture Behavioral of SerialReceiver is
 
 signal cmd_received_sig : STD_LOGIC := '0';
 signal rxs : STD_LOGIC := '0';
-signal rxs2 : STD_LOGIC := '0';
+signal rx_delay_line: STD_LOGIC_VECTOR(5 downto 0);
 signal serial_data : STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
 signal serial_counter : STD_LOGIC_VECTOR (9 downto 0) := (others => '0');
 --baud rate: 115200
@@ -45,14 +45,9 @@ begin
 sanitize_input: process(clk100)
 begin
 	if rising_edge(clk100) then
-		rxs <= rxs2;
-	end if;
-end process;
-
-sanitize_input2: process(clk100)
-begin
-	if rising_edge(clk100) then
-		rxs2 <= s_data_in;
+		rx_delay_line(5) <= s_data_in;
+		rx_delay_line(4 downto 0) <= rx_delay_line(5 downto 1);
+		rxs <= rx_delay_line(0);
 	end if;
 end process;
 
@@ -68,7 +63,7 @@ begin
 				serial_counter <= (others => '0');
 				serial_data(8 downto 0) <= serial_data(9 downto 1);
 				serial_data(9) <= NOT rxs;
-				cmd_received_sig <= not serial_data(1); --this should maybe be serial_data(0)
+				cmd_received_sig <= not serial_data(1); --this should maybe be serial_data(0) update: no, i think this is correct.
 			else
 				serial_counter <= serial_counter + 1;
 				cmd_received_sig <= '0';