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Commit 07bd8bee authored by Pascal Engeler's avatar Pascal Engeler
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Added LockinChain testbench implementation

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stitch_project/stitch/LockinChainTestbench.vhd 0 → 100644
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:22:34 12/02/2024
-- Design Name:
-- Module Name: /home/ise/iseprojects/stitch/stitch_project/stitch/LockinChainTestbench.vhd
-- Project Name: stitch
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: LockinChain
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY LockinChainTestbench IS
END LockinChainTestbench;
ARCHITECTURE behavior OF LockinChainTestbench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT LockinChain
PORT(
CLK100 : IN std_logic;
PHI : OUT std_logic_vector(31 downto 0);
CORDIC_COS : OUT std_logic_vector(20 downto 0);
CORDIC_SIN : OUT std_logic_vector(20 downto 0);
UNWRAPPER_DISTANCE : OUT std_logic_vector(24 downto 0);
UNWRAPPER_DR : OUT std_logic;
LOCKIN_DATACOS : OUT std_logic_vector(63 downto 0);
LOCKIN_DATASIN : OUT std_logic_vector(63 downto 0);
LOCKIN_NSAMPLES : OUT std_logic_vector(31 downto 0);
LOCKIN_IDLE : OUT std_logic;
LOCKIN_EN : OUT std_logic;
LOCKIN_CLEAR : OUT std_logic;
SWEEPER_AMP_MEM_ADDR : OUT std_logic_vector(9 downto 0);
SWEEPER_SAMPLES_MEM_ADDR : OUT std_logic_vector(9 downto 0);
SWEEPER_WR_EN : OUT std_logic;
SWEEPER_start : IN std_logic;
SWEEPER_n_freqs : IN std_logic_vector(9 downto 0);
SWEEPER_ddphi_mem_rd_data : IN std_logic_vector(22 downto 0);
SWEEPER_dphi_mem_rd_data : IN std_logic_vector(22 downto 0);
SWEEPER_n_ringup_mem_rd_data : IN std_logic_vector(31 downto 0);
SWEEPER_n_meas_mem_rd_data : IN std_logic_vector(31 downto 0);
SWEEPER_n_sweep_mem_rd_data : IN std_logic_vector(31 downto 0);
UNWRAPPER_distance_in : IN std_logic_vector(20 downto 0);
UNWRAPPER_dr_in : IN std_logic;
SWEEPER_ddphi_mem_rd_addr : OUT std_logic_vector(9 downto 0);
SWEEPER_dphi_mem_rd_addr : OUT std_logic_vector(9 downto 0);
SWEEPER_n_ringup_mem_rd_addr : OUT std_logic_vector(9 downto 0);
SWEEPER_n_meas_mem_rd_addr : OUT std_logic_vector(9 downto 0);
SWEEPER_n_sweep_mem_rd_addr : OUT std_logic_vector(9 downto 0)
);
END COMPONENT;
--Inputs
signal CLK100 : std_logic := '0';
signal SWEEPER_start : std_logic := '0';
signal SWEEPER_n_freqs : std_logic_vector(9 downto 0) := (others => '0');
signal SWEEPER_ddphi_mem_rd_data : std_logic_vector(22 downto 0) := (others => '0');
signal SWEEPER_dphi_mem_rd_data : std_logic_vector(22 downto 0) := (others => '0');
signal SWEEPER_n_ringup_mem_rd_data : std_logic_vector(31 downto 0) := (others => '0');
signal SWEEPER_n_meas_mem_rd_data : std_logic_vector(31 downto 0) := (others => '0');
signal SWEEPER_n_sweep_mem_rd_data : std_logic_vector(31 downto 0) := (others => '0');
signal UNWRAPPER_distance_in : std_logic_vector(20 downto 0) := (others => '0');
signal UNWRAPPER_dr_in : std_logic := '0';
--Outputs
signal PHI : std_logic_vector(31 downto 0);
signal CORDIC_COS : std_logic_vector(20 downto 0);
signal CORDIC_SIN : std_logic_vector(20 downto 0);
signal UNWRAPPER_DISTANCE : std_logic_vector(24 downto 0);
signal UNWRAPPER_DR : std_logic;
signal LOCKIN_DATACOS : std_logic_vector(63 downto 0);
signal LOCKIN_DATASIN : std_logic_vector(63 downto 0);
signal LOCKIN_NSAMPLES : std_logic_vector(31 downto 0);
signal LOCKIN_IDLE : std_logic;
signal LOCKIN_EN : std_logic;
signal LOCKIN_CLEAR : std_logic;
signal SWEEPER_AMP_MEM_ADDR : std_logic_vector(9 downto 0);
signal SWEEPER_SAMPLES_MEM_ADDR : std_logic_vector(9 downto 0);
signal SWEEPER_WR_EN : std_logic;
signal SWEEPER_ddphi_mem_rd_addr : std_logic_vector(9 downto 0);
signal SWEEPER_dphi_mem_rd_addr : std_logic_vector(9 downto 0);
signal SWEEPER_n_ringup_mem_rd_addr : std_logic_vector(9 downto 0);
signal SWEEPER_n_meas_mem_rd_addr : std_logic_vector(9 downto 0);
signal SWEEPER_n_sweep_mem_rd_addr : std_logic_vector(9 downto 0);
-- Clock period definitions
constant CLK100_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: LockinChain PORT MAP (
CLK100 => CLK100,
PHI => PHI,
CORDIC_COS => CORDIC_COS,
CORDIC_SIN => CORDIC_SIN,
UNWRAPPER_DISTANCE => UNWRAPPER_DISTANCE,
UNWRAPPER_DR => UNWRAPPER_DR,
LOCKIN_DATACOS => LOCKIN_DATACOS,
LOCKIN_DATASIN => LOCKIN_DATASIN,
LOCKIN_NSAMPLES => LOCKIN_NSAMPLES,
LOCKIN_IDLE => LOCKIN_IDLE,
LOCKIN_EN => LOCKIN_EN,
LOCKIN_CLEAR => LOCKIN_CLEAR,
SWEEPER_AMP_MEM_ADDR => SWEEPER_AMP_MEM_ADDR,
SWEEPER_SAMPLES_MEM_ADDR => SWEEPER_SAMPLES_MEM_ADDR,
SWEEPER_WR_EN => SWEEPER_WR_EN,
SWEEPER_start => SWEEPER_start,
SWEEPER_n_freqs => SWEEPER_n_freqs,
SWEEPER_ddphi_mem_rd_data => SWEEPER_ddphi_mem_rd_data,
SWEEPER_dphi_mem_rd_data => SWEEPER_dphi_mem_rd_data,
SWEEPER_n_ringup_mem_rd_data => SWEEPER_n_ringup_mem_rd_data,
SWEEPER_n_meas_mem_rd_data => SWEEPER_n_meas_mem_rd_data,
SWEEPER_n_sweep_mem_rd_data => SWEEPER_n_sweep_mem_rd_data,
UNWRAPPER_distance_in => UNWRAPPER_distance_in,
UNWRAPPER_dr_in => UNWRAPPER_dr_in,
SWEEPER_ddphi_mem_rd_addr => SWEEPER_ddphi_mem_rd_addr,
SWEEPER_dphi_mem_rd_addr => SWEEPER_dphi_mem_rd_addr,
SWEEPER_n_ringup_mem_rd_addr => SWEEPER_n_ringup_mem_rd_addr,
SWEEPER_n_meas_mem_rd_addr => SWEEPER_n_meas_mem_rd_addr,
SWEEPER_n_sweep_mem_rd_addr => SWEEPER_n_sweep_mem_rd_addr
);
-- Clock process definitions
CLK100_process :process
begin
CLK100 <= '0';
wait for CLK100_period/2;
CLK100 <= '1';
wait for CLK100_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
SWEEPER_start <= '0';
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK100_period*10;
-- insert stimulus here
SWEEPER_n_freqs <= "0000000010";
SWEEPER_start <= '1';
wait for 50ns;
SWEEPER_start <= '0';
wait;
end process;
-- Interferometer process
infr_proc: process
begin
--can program longer laser traces here, which will just be repeated
--can also use IFs to make them dependent on dphi
UNWRAPPER_distance_in <= "000110101100110010100";
UNWRAPPER_DR <= '0';
wait for 840 ns;
UNWRAPPER_DR <= '1';
wait for 70 ns;
end process;
-- Memory process
mem_proc: process
begin
--mem_dphi
if SWEEPER_dphi_mem_rd_addr = "0000000000" then
SWEEPER_dphi_mem_rd_data <= "00000000000101001111100";
elsif SWEEPER_dphi_mem_rd_addr = "0000000001" then
SWEEPER_dphi_mem_rd_data <= "00001111100100001001011";
else
SWEEPER_dphi_mem_rd_data <= "00011000100100110111010";
end if;
--mem_ddphi
SWEEPER_ddphi_mem_rd_data <= "00011011011111001101111";
--mem_n_ringup
if SWEEPER_n_ringup_mem_rd_addr = "0000000000" then
SWEEPER_n_ringup_mem_rd_data <= "00000101111101011110000100000000";
elsif SWEEPER_n_ringup_mem_rd_addr = "0000000001" then
SWEEPER_n_ringup_mem_rd_data <= "00000000000010000000011111101011";
else
SWEEPER_n_ringup_mem_rd_data <= "00000000000001010001011000010101";
end if;
--mem_n_sweep
if SWEEPER_n_sweep_mem_rd_addr = "0000000000" then
SWEEPER_n_sweep_mem_rd_data <= "00000000000000000000000000000000";
elsif SWEEPER_n_sweep_mem_rd_addr = "0000000001" then
SWEEPER_n_sweep_mem_rd_data <= "00000000010010000001100100001100";
else
SWEEPER_n_sweep_mem_rd_data <= "00000000001010011111011000110010";
end if;
--mem_n_meas
if SWEEPER_n_ringup_mem_rd_addr = "0000000000" then
SWEEPER_n_meas_mem_rd_data <= "00000101111101011110000100000000";
elsif SWEEPER_n_ringup_mem_rd_addr = "0000000001" then
SWEEPER_n_meas_mem_rd_data <= "00000000000010000000011111101011";
else
SWEEPER_n_meas_mem_rd_data <= "00000000000001010001011000010101";
end if;
end process;
END;
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