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Pascal Engeler
Bridge_FPGA_RAM
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c8417cc16ee3f6f0fc39666150e9a26664f909c1
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1-approach-1
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Created with Raphaël 2.2.0
21
Sep
8
7
debugging on windows done, it works with a few issues.
1-approach-1
1-approach-1
Bug fixes, changed commands 58 and 61
added strobing
Changed bus widths (rP, tSC, tEI), changed bit layout of cmd 60 response
Changed recordingPointer end criterion
removed memoryReadAddress and memoryWriteAddress
Added analysis files
Added initial values to carli signals
master
master
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