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This is an archived project. Repository and other project resources are read-only.

Oliver Wipfli
simon-lab-fir

S

simon-lab-fir Archived

Project information

Finite Impulse Response (FIR) filter implemented on a Red Pitaya FPGA based on a project from the Simon Lab.

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README

Created on

November 26, 2019

Copy SSH clone URLgit@gitlab.phys.ethz.ch:wipfli/simon-lab-fir.git
Copy HTTPS clone URLhttps://gitlab.phys.ethz.ch/wipfli/simon-lab-fir.git