diff --git a/stitch_project/stitch/Stitch.bin b/stitch_project/stitch/Stitch.bin
index f7ee4580d99888835ad06d06b05fe66f5958d5e1..95951a882f31cb2f0dac295c36bbf3b420c4deb6 100644
Binary files a/stitch_project/stitch/Stitch.bin and b/stitch_project/stitch/Stitch.bin differ
diff --git a/stitch_project/stitch/_xmsgs/pn_parser.xmsgs b/stitch_project/stitch/_xmsgs/pn_parser.xmsgs
index a38ed26047276d5bf92a23d9e4339a8fd78998bd..89c3627e5f1e3a9ca3320e655157b3225ac56953 100644
--- a/stitch_project/stitch/_xmsgs/pn_parser.xmsgs
+++ b/stitch_project/stitch/_xmsgs/pn_parser.xmsgs
@@ -8,5 +8,8 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
+<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/ise/iseprojects/stitch/stitch_project/stitch/LockInAccumulator.vhd" into library work</arg>
+</msg>
+
</messages>
diff --git a/stitch_project/stitch/ipcore_dir/Mem32b1024.gise b/stitch_project/stitch/ipcore_dir/Mem32b1024.gise
index 2d90edb54ec2b229b50ef838f83de185ebafc1b7..2abcc8ec1f2d42766f49c317417612a22fe5c9fa 100644
--- a/stitch_project/stitch/ipcore_dir/Mem32b1024.gise
+++ b/stitch_project/stitch/ipcore_dir/Mem32b1024.gise
@@ -32,19 +32,19 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3185129189393661258" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3185129189393661258" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7316991560476725013" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7316991560476725013" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-4997764571106617334" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-4997764571106617334" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
diff --git a/stitch_project/stitch/ipcore_dir/MemNsamp.gise b/stitch_project/stitch/ipcore_dir/MemNsamp.gise
index 6feaef48ff0126819964739a77581663c53fd3fe..981007879a7831942ed1343ce55c8898974a760f 100644
--- a/stitch_project/stitch/ipcore_dir/MemNsamp.gise
+++ b/stitch_project/stitch/ipcore_dir/MemNsamp.gise
@@ -32,19 +32,19 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-6820686459059339956" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-6820686459059339956" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-7915863299109585449" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-7915863299109585449" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="5925673752377620492" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="5925673752377620492" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
diff --git a/stitch_project/stitch/ipcore_dir/MemSinCos.gise b/stitch_project/stitch/ipcore_dir/MemSinCos.gise
index 362b1f23dd097cd90906419c96c654b14adfeeab..2487487c48afdf0a59709682db34552bf0979006 100644
--- a/stitch_project/stitch/ipcore_dir/MemSinCos.gise
+++ b/stitch_project/stitch/ipcore_dir/MemSinCos.gise
@@ -32,19 +32,19 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-2788987222142637780" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-2788987222142637780" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="4978056458918207415" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="4978056458918207415" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6045739603124474860" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6045739603124474860" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
diff --git a/stitch_project/stitch/ipcore_dir/cordic.gise b/stitch_project/stitch/ipcore_dir/cordic.gise
index d3d8c1d44b5cea40b157590d4d613450d11a441e..aa96bc636136e3236c71072e2746fc40d9359a53 100644
--- a/stitch_project/stitch/ipcore_dir/cordic.gise
+++ b/stitch_project/stitch/ipcore_dir/cordic.gise
@@ -32,19 +32,19 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8782926585333300168" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8782926585333300168" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7818039811878659395" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7818039811878659395" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3776669437272252152" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3776669437272252152" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
diff --git a/stitch_project/stitch/ipcore_dir/multiaddCos.gise b/stitch_project/stitch/ipcore_dir/multiaddCos.gise
index 0839c246f0447811a31a01ddb9370d217e42e430..745956cedbaff6b9344cf44161e7578468979ea3 100644
--- a/stitch_project/stitch/ipcore_dir/multiaddCos.gise
+++ b/stitch_project/stitch/ipcore_dir/multiaddCos.gise
@@ -34,19 +34,19 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="5836199371156688706" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-6854975743064405440" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-7361811691951278067" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8175489371127869360" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="4442281788066732546" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="4442281788066732546" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
diff --git a/stitch_project/stitch/ipcore_dir/multiaddSin.gise b/stitch_project/stitch/ipcore_dir/multiaddSin.gise
index 8a14d92054825042aa3ca6702d9801d97d99775a..36e3ecd2d067cdaf03214a707d5cf5487d797b64 100644
--- a/stitch_project/stitch/ipcore_dir/multiaddSin.gise
+++ b/stitch_project/stitch/ipcore_dir/multiaddSin.gise
@@ -34,19 +34,19 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-4086567091452493108" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-4086567091452493108" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-442521152817317545" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-442521152817317545" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724680524" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5480484674542449268" xil_pn:start_ts="1724680524">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5480484674542449268" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
diff --git a/stitch_project/stitch/stitch.gise b/stitch_project/stitch/stitch.gise
index 3c41dc10b3f088fb035f52ef84f47a8fff593bd4..14a9d20d800337a1394b20a4f5e99167a036136d 100644
--- a/stitch_project/stitch/stitch.gise
+++ b/stitch_project/stitch/stitch.gise
@@ -137,15 +137,15 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
- <transform xil_pn:end_ts="1720131871" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1720131871">
+ <transform xil_pn:end_ts="1719628948" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1719628948">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724683433" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1000327047199651568" xil_pn:start_ts="1724683433">
+ <transform xil_pn:end_ts="1719628948" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1000327047199651568" xil_pn:start_ts="1719628948">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719627900" xil_pn:in_ck="-759697606739902482" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2646617551451894976" xil_pn:start_ts="1719627898">
+ <transform xil_pn:end_ts="1719628949" xil_pn:in_ck="-759697606739902482" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2646617551451894976" xil_pn:start_ts="1719628948">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ipcore_dir/Mem32b1024.ngc"/>
@@ -161,23 +161,23 @@
<outfile xil_pn:name="ipcore_dir/multiaddSin.ngc"/>
<outfile xil_pn:name="ipcore_dir/multiaddSin.vhd"/>
</transform>
- <transform xil_pn:name="TRAN_SubProjectAbstractToPreProxy">
+ <transform xil_pn:end_ts="1719628949" xil_pn:in_ck="6231951733186561032" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724683435" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-7265130963783582190" xil_pn:start_ts="1724683435">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-7265130963783582190" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724683435" xil_pn:in_ck="6231951733186561032" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1724683435">
+ <transform xil_pn:end_ts="1719628949" xil_pn:in_ck="6231951733186561032" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1724683435" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-3892313077777873078" xil_pn:start_ts="1724683435">
+ <transform xil_pn:end_ts="1719628949" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-3892313077777873078" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719627909" xil_pn:in_ck="5188678245468887340" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-6684372598054868263" xil_pn:start_ts="1719627900">
+ <transform xil_pn:end_ts="1719628959" xil_pn:in_ck="5188678245468887340" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-6684372598054868263" xil_pn:start_ts="1719628949">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -195,11 +195,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
- <transform xil_pn:end_ts="1724683484" xil_pn:in_ck="5505092852261115" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3812858228316398073" xil_pn:start_ts="1724683484">
+ <transform xil_pn:end_ts="1719628959" xil_pn:in_ck="5505092852261115" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3812858228316398073" xil_pn:start_ts="1719628959">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719627913" xil_pn:in_ck="-9033868516707283598" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="230146358404850379" xil_pn:start_ts="1719627909">
+ <transform xil_pn:end_ts="1719628963" xil_pn:in_ck="-9033868516707283598" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="230146358404850379" xil_pn:start_ts="1719628959">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Stitch.bld"/>
@@ -208,7 +208,7 @@
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
- <transform xil_pn:end_ts="1719627928" xil_pn:in_ck="-4325218870543059951" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-398923363910175968" xil_pn:start_ts="1719627913">
+ <transform xil_pn:end_ts="1719628986" xil_pn:in_ck="-4325218870543059951" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-398923363910175968" xil_pn:start_ts="1719628963">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -222,7 +222,7 @@
<outfile xil_pn:name="Stitch_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
- <transform xil_pn:end_ts="1719627946" xil_pn:in_ck="-6627939747938971286" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1719627928">
+ <transform xil_pn:end_ts="1719629005" xil_pn:in_ck="-6627939747938971286" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1719628986">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Stitch.ncd"/>
@@ -236,7 +236,7 @@
<outfile xil_pn:name="Stitch_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform>
- <transform xil_pn:end_ts="1719627952" xil_pn:in_ck="4019925351390994" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="4970201210546912173" xil_pn:start_ts="1719627946">
+ <transform xil_pn:end_ts="1719629011" xil_pn:in_ck="4019925351390994" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="4970201210546912173" xil_pn:start_ts="1719629005">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -249,7 +249,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
- <transform xil_pn:end_ts="1719627946" xil_pn:in_ck="-4527387296597967219" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1719627941">
+ <transform xil_pn:end_ts="1719629005" xil_pn:in_ck="-4527387296597967219" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1719629000">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Stitch.twr"/>
diff --git a/stitch_project/stitch/xst/work/work.vdbl b/stitch_project/stitch/xst/work/work.vdbl
index b0761ba5961f4c170a2eed10f7254846f42e3198..05b28881de293d7277cc4def665f85383dec4645 100644
Binary files a/stitch_project/stitch/xst/work/work.vdbl and b/stitch_project/stitch/xst/work/work.vdbl differ
diff --git a/stitch_project/stitch/xst/work/work.vdbx b/stitch_project/stitch/xst/work/work.vdbx
index 8689d7617ca22abe2571f8495c11877dfbc04871..2d131e1d409fb0fa09fc0785e8ebf1c180688546 100644
Binary files a/stitch_project/stitch/xst/work/work.vdbx and b/stitch_project/stitch/xst/work/work.vdbx differ