diff --git a/stitch_project/stitch/Stitch.bin b/stitch_project/stitch/Stitch.bin
index 9bb3fe2ab7eb175b86090a452d8c94252b50df1a..8d4c004b70b47e31ac1f6115a9baf57aa7643d60 100644
Binary files a/stitch_project/stitch/Stitch.bin and b/stitch_project/stitch/Stitch.bin differ
diff --git a/stitch_project/stitch/Stitch.vhd b/stitch_project/stitch/Stitch.vhd
index f438a9cd200dc22f6bdfb188474f9d4425d40ed0..ca2cf883b759d8b36bf5d8b8af82e0ed5e675e88 100644
--- a/stitch_project/stitch/Stitch.vhd
+++ b/stitch_project/stitch/Stitch.vhd
@@ -332,6 +332,10 @@ PORT (
);
END COMPONENT;
+--signals to detect unwrapping
+signal or_24_23 : STD_LOGIC;
+signal or_22_21 : STD_LOGIC;
+
begin
-- route signals here
@@ -429,7 +433,10 @@ DDS_OUT <= iSweeper_phi(28);
--LEDS(0) <= '1';
LEDS(0) <= iDistanceUnwrapper_dr_out;
LEDS(1) <= NOT iSweeper_idle;
-LEDS(2) <= NOT iReadbackControl_idle;
+--LEDS(2) <= NOT iReadbackControl_idle;
+or_24_23 <= iDistanceUnwrapper_distance_out(24) OR iDistanceUnwrapper_distance_out(23);
+or_22_21 <= iDistanceUnwrapper_distance_out(22) OR iDistanceUnwrapper_distance_out(21);
+LEDS(2) <= or_24_23 OR or_22_21;
phi_clean(31 downto 1) <= iSweeper_phi(30 downto 0);
phi_clean(0) <= '0';
diff --git a/stitch_project/stitch/ipcore_dir/Mem32b1024.gise b/stitch_project/stitch/ipcore_dir/Mem32b1024.gise
index 53db3de33b9719e11e78ff3291c6fff0beaee3c3..830ccb29bfef980f8a22e3f7dbab1899d5ce2239 100644
--- a/stitch_project/stitch/ipcore_dir/Mem32b1024.gise
+++ b/stitch_project/stitch/ipcore_dir/Mem32b1024.gise
@@ -32,19 +32,19 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3185129189393661258" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3185129189393661258" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7316991560476725013" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7316991560476725013" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-4997764571106617334" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-4997764571106617334" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
diff --git a/stitch_project/stitch/ipcore_dir/MemNsamp.gise b/stitch_project/stitch/ipcore_dir/MemNsamp.gise
index 0b30c6bceb735cb62c1f222670afdfe698de8111..20bca32e67b1d269e300cf29da9104cb89793513 100644
--- a/stitch_project/stitch/ipcore_dir/MemNsamp.gise
+++ b/stitch_project/stitch/ipcore_dir/MemNsamp.gise
@@ -32,19 +32,19 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-6820686459059339956" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-6820686459059339956" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-7915863299109585449" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-7915863299109585449" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="5925673752377620492" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="5925673752377620492" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
diff --git a/stitch_project/stitch/ipcore_dir/MemSinCos.gise b/stitch_project/stitch/ipcore_dir/MemSinCos.gise
index 4c616af038a4c4791588d0310ecbb054fb9110c7..fa0f8d8fc0dd776e65d89c0c95750b8c4bf5f0c6 100644
--- a/stitch_project/stitch/ipcore_dir/MemSinCos.gise
+++ b/stitch_project/stitch/ipcore_dir/MemSinCos.gise
@@ -32,19 +32,19 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-2788987222142637780" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-2788987222142637780" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="4978056458918207415" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="4978056458918207415" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6045739603124474860" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6045739603124474860" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
diff --git a/stitch_project/stitch/ipcore_dir/cordic.gise b/stitch_project/stitch/ipcore_dir/cordic.gise
index 956e73f881dac77c60870589d431cab89542e113..bed77bfa79f4bf499f0e731f401a51467a5bb227 100644
--- a/stitch_project/stitch/ipcore_dir/cordic.gise
+++ b/stitch_project/stitch/ipcore_dir/cordic.gise
@@ -32,19 +32,19 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8782926585333300168" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8782926585333300168" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7818039811878659395" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7818039811878659395" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3776669437272252152" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3776669437272252152" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
diff --git a/stitch_project/stitch/ipcore_dir/multiaddCos.gise b/stitch_project/stitch/ipcore_dir/multiaddCos.gise
index 88153d16081f6b1497089a329c323507d75f5a04..292844d3ce5310a9d8d325683b51777ec3dbbedd 100644
--- a/stitch_project/stitch/ipcore_dir/multiaddCos.gise
+++ b/stitch_project/stitch/ipcore_dir/multiaddCos.gise
@@ -34,19 +34,19 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-6854975743064405440" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-6854975743064405440" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8175489371127869360" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8175489371127869360" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="4442281788066732546" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="4442281788066732546" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
diff --git a/stitch_project/stitch/ipcore_dir/multiaddSin.gise b/stitch_project/stitch/ipcore_dir/multiaddSin.gise
index 857db549fe1e010752a54ed61a659a59b65321b0..d791298ee243f5a03eb6d3ca17f0eba423675989 100644
--- a/stitch_project/stitch/ipcore_dir/multiaddSin.gise
+++ b/stitch_project/stitch/ipcore_dir/multiaddSin.gise
@@ -34,19 +34,19 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1669001868035964362" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1669001868035964362" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-3351964163447721734" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-3351964163447721734" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5480484674542449268" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5480484674542449268" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
diff --git a/stitch_project/stitch/stitch.gise b/stitch_project/stitch/stitch.gise
index 6701972267ba6fa2eda02ef70ec0271f49d0221c..50ede3569007cec6a47d0e44d47edd611758c530 100644
--- a/stitch_project/stitch/stitch.gise
+++ b/stitch_project/stitch/stitch.gise
@@ -137,15 +137,15 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
- <transform xil_pn:end_ts="1719695019" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1719695019">
+ <transform xil_pn:end_ts="1726124436" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1726124436">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695019" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1000327047199651568" xil_pn:start_ts="1719695019">
+ <transform xil_pn:end_ts="1726124436" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1000327047199651568" xil_pn:start_ts="1726124436">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:in_ck="-759697606739902482" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2646617551451894976" xil_pn:start_ts="1719695019">
+ <transform xil_pn:end_ts="1726124439" xil_pn:in_ck="-759697606739902482" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2646617551451894976" xil_pn:start_ts="1726124436">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ipcore_dir/Mem32b1024.ngc"/>
@@ -161,28 +161,30 @@
<outfile xil_pn:name="ipcore_dir/multiaddSin.ngc"/>
<outfile xil_pn:name="ipcore_dir/multiaddSin.vhd"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:in_ck="6231951733186561032" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:in_ck="6231951733186561032" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-7265130963783582190" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-7265130963783582190" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:in_ck="6231951733186561032" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:in_ck="6231951733186561032" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-3892313077777873078" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124439" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-3892313077777873078" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695033" xil_pn:in_ck="-2009185075857292629" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-6684372598054868263" xil_pn:start_ts="1719695020">
+ <transform xil_pn:end_ts="1726124519" xil_pn:in_ck="-2009185075857292629" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-6684372598054868263" xil_pn:start_ts="1726124439">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
+ <outfile xil_pn:name="CommandDecoder.ngr"/>
+ <outfile xil_pn:name="ReadbackControl.ngr"/>
<outfile xil_pn:name="Stitch.lso"/>
<outfile xil_pn:name="Stitch.ngc"/>
<outfile xil_pn:name="Stitch.ngr"/>
@@ -191,15 +193,16 @@
<outfile xil_pn:name="Stitch.syr"/>
<outfile xil_pn:name="Stitch.xst"/>
<outfile xil_pn:name="Stitch_xst.xrpt"/>
+ <outfile xil_pn:name="Sweeper.ngr"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
- <transform xil_pn:end_ts="1719695033" xil_pn:in_ck="5505092852261115" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3812858228316398073" xil_pn:start_ts="1719695033">
+ <transform xil_pn:end_ts="1726124519" xil_pn:in_ck="5505092852261115" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3812858228316398073" xil_pn:start_ts="1726124519">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719695037" xil_pn:in_ck="-9033868516707283598" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="230146358404850379" xil_pn:start_ts="1719695033">
+ <transform xil_pn:end_ts="1726124539" xil_pn:in_ck="3802728747819461154" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="230146358404850379" xil_pn:start_ts="1726124519">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Stitch.bld"/>
@@ -208,7 +211,7 @@
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
- <transform xil_pn:end_ts="1719695054" xil_pn:in_ck="-4325218870543059951" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-398923363910175968" xil_pn:start_ts="1719695037">
+ <transform xil_pn:end_ts="1726124653" xil_pn:in_ck="-3282794330040821884" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-398923363910175968" xil_pn:start_ts="1726124539">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -222,7 +225,7 @@
<outfile xil_pn:name="Stitch_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
- <transform xil_pn:end_ts="1719695073" xil_pn:in_ck="-6627939747938971286" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1719695054">
+ <transform xil_pn:end_ts="1726124766" xil_pn:in_ck="-8255871056631862401" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1726124653">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Stitch.ncd"/>
@@ -236,7 +239,7 @@
<outfile xil_pn:name="Stitch_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform>
- <transform xil_pn:end_ts="1719695080" xil_pn:in_ck="4019925351390994" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="4970201210546912173" xil_pn:start_ts="1719695073">
+ <transform xil_pn:end_ts="1726124805" xil_pn:in_ck="6552744863914881674" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="4970201210546912173" xil_pn:start_ts="1726124766">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -249,7 +252,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
- <transform xil_pn:end_ts="1719695073" xil_pn:in_ck="-4527387296597967219" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1719695068">
+ <transform xil_pn:end_ts="1726124766" xil_pn:in_ck="3901311056773105669" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1726124741">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Stitch.twr"/>
diff --git a/stitch_project/stitch/xst/work/work.vdbl b/stitch_project/stitch/xst/work/work.vdbl
index 6cce3b321b17da434d158f14c979fce7a12f418e..83081686e373a2de7e5eedac8168e4463f63ef88 100644
Binary files a/stitch_project/stitch/xst/work/work.vdbl and b/stitch_project/stitch/xst/work/work.vdbl differ
diff --git a/stitch_project/stitch/xst/work/work.vdbx b/stitch_project/stitch/xst/work/work.vdbx
index 64b0053bf2ae14293e394dd597f4f0fc595ea655..7c6bd99dbe7e7fd4a28593326bd1a3fd72ed5636 100644
Binary files a/stitch_project/stitch/xst/work/work.vdbx and b/stitch_project/stitch/xst/work/work.vdbx differ