From 4e506671fea858c8680b4bf8c643546a3eb8d5f4 Mon Sep 17 00:00:00 2001
From: Pascal Engeler <engelerp@phys.ethz.ch>
Date: Wed, 11 Sep 2024 13:10:05 +0200
Subject: [PATCH] Autogenerated file changes
---
stitch_project/stitch/_xmsgs/pn_parser.xmsgs | 2 +-
.../stitch/ipcore_dir/Mem32b1024.gise | 8 ++---
.../stitch/ipcore_dir/MemNsamp.gise | 8 ++---
.../stitch/ipcore_dir/MemSinCos.gise | 8 ++---
stitch_project/stitch/ipcore_dir/cordic.gise | 8 ++---
.../stitch/ipcore_dir/multiaddCos.gise | 8 ++---
.../stitch/ipcore_dir/multiaddSin.gise | 8 ++---
stitch_project/stitch/stitch.gise | 28 +++++++++---------
stitch_project/stitch/xst/work/work.vdbl | Bin 305822 -> 305844 bytes
stitch_project/stitch/xst/work/work.vdbx | Bin 431 -> 431 bytes
10 files changed, 39 insertions(+), 39 deletions(-)
diff --git a/stitch_project/stitch/_xmsgs/pn_parser.xmsgs b/stitch_project/stitch/_xmsgs/pn_parser.xmsgs
index 7844eae..4cdaa97 100644
--- a/stitch_project/stitch/_xmsgs/pn_parser.xmsgs
+++ b/stitch_project/stitch/_xmsgs/pn_parser.xmsgs
@@ -8,7 +8,7 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
-<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/ise/iseprojects/stitch/stitch_project/stitch/DistanceUnwrapper.vhd" into library work</arg>
+<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/ise/iseprojects/stitch/stitch_project/stitch/Stitch.vhd" into library work</arg>
</msg>
</messages>
diff --git a/stitch_project/stitch/ipcore_dir/Mem32b1024.gise b/stitch_project/stitch/ipcore_dir/Mem32b1024.gise
index bd8e3bf..53db3de 100644
--- a/stitch_project/stitch/ipcore_dir/Mem32b1024.gise
+++ b/stitch_project/stitch/ipcore_dir/Mem32b1024.gise
@@ -32,19 +32,19 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3185129189393661258" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3185129189393661258" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7316991560476725013" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7316991560476725013" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-4997764571106617334" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-4997764571106617334" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
diff --git a/stitch_project/stitch/ipcore_dir/MemNsamp.gise b/stitch_project/stitch/ipcore_dir/MemNsamp.gise
index df6a9b6..0b30c6b 100644
--- a/stitch_project/stitch/ipcore_dir/MemNsamp.gise
+++ b/stitch_project/stitch/ipcore_dir/MemNsamp.gise
@@ -32,19 +32,19 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-6820686459059339956" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-6820686459059339956" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-7915863299109585449" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-7915863299109585449" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="5925673752377620492" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="5925673752377620492" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
diff --git a/stitch_project/stitch/ipcore_dir/MemSinCos.gise b/stitch_project/stitch/ipcore_dir/MemSinCos.gise
index 7c1b8e1..4c616af 100644
--- a/stitch_project/stitch/ipcore_dir/MemSinCos.gise
+++ b/stitch_project/stitch/ipcore_dir/MemSinCos.gise
@@ -32,19 +32,19 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-2788987222142637780" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-2788987222142637780" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="4978056458918207415" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="4978056458918207415" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6045739603124474860" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6045739603124474860" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
diff --git a/stitch_project/stitch/ipcore_dir/cordic.gise b/stitch_project/stitch/ipcore_dir/cordic.gise
index 4cd62bd..956e73f 100644
--- a/stitch_project/stitch/ipcore_dir/cordic.gise
+++ b/stitch_project/stitch/ipcore_dir/cordic.gise
@@ -32,19 +32,19 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8782926585333300168" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-8782926585333300168" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7818039811878659395" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7818039811878659395" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3776669437272252152" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3776669437272252152" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
diff --git a/stitch_project/stitch/ipcore_dir/multiaddCos.gise b/stitch_project/stitch/ipcore_dir/multiaddCos.gise
index 6d69dbd..88153d1 100644
--- a/stitch_project/stitch/ipcore_dir/multiaddCos.gise
+++ b/stitch_project/stitch/ipcore_dir/multiaddCos.gise
@@ -34,19 +34,19 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-6854975743064405440" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-6854975743064405440" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8175489371127869360" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8175489371127869360" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="4442281788066732546" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="4442281788066732546" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
diff --git a/stitch_project/stitch/ipcore_dir/multiaddSin.gise b/stitch_project/stitch/ipcore_dir/multiaddSin.gise
index 6e3a992..857db54 100644
--- a/stitch_project/stitch/ipcore_dir/multiaddSin.gise
+++ b/stitch_project/stitch/ipcore_dir/multiaddSin.gise
@@ -34,19 +34,19 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1669001868035964362" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1669001868035964362" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-3351964163447721734" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-3351964163447721734" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5480484674542449268" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5480484674542449268" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
diff --git a/stitch_project/stitch/stitch.gise b/stitch_project/stitch/stitch.gise
index ed33937..6701972 100644
--- a/stitch_project/stitch/stitch.gise
+++ b/stitch_project/stitch/stitch.gise
@@ -137,15 +137,15 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
- <transform xil_pn:end_ts="1719693565" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1719693565">
+ <transform xil_pn:end_ts="1719695019" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1719695019">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693565" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1000327047199651568" xil_pn:start_ts="1719693565">
+ <transform xil_pn:end_ts="1719695019" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1000327047199651568" xil_pn:start_ts="1719695019">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:in_ck="-759697606739902482" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2646617551451894976" xil_pn:start_ts="1719693565">
+ <transform xil_pn:end_ts="1719695020" xil_pn:in_ck="-759697606739902482" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2646617551451894976" xil_pn:start_ts="1719695019">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ipcore_dir/Mem32b1024.ngc"/>
@@ -161,23 +161,23 @@
<outfile xil_pn:name="ipcore_dir/multiaddSin.ngc"/>
<outfile xil_pn:name="ipcore_dir/multiaddSin.vhd"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:in_ck="6231951733186561032" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:in_ck="6231951733186561032" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-7265130963783582190" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-7265130963783582190" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:in_ck="6231951733186561032" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:in_ck="6231951733186561032" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693566" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-3892313077777873078" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695020" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-3892313077777873078" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693578" xil_pn:in_ck="-2009185075857292629" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-6684372598054868263" xil_pn:start_ts="1719693566">
+ <transform xil_pn:end_ts="1719695033" xil_pn:in_ck="-2009185075857292629" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-6684372598054868263" xil_pn:start_ts="1719695020">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -195,11 +195,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
- <transform xil_pn:end_ts="1719693578" xil_pn:in_ck="5505092852261115" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3812858228316398073" xil_pn:start_ts="1719693578">
+ <transform xil_pn:end_ts="1719695033" xil_pn:in_ck="5505092852261115" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3812858228316398073" xil_pn:start_ts="1719695033">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
- <transform xil_pn:end_ts="1719693582" xil_pn:in_ck="-9033868516707283598" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="230146358404850379" xil_pn:start_ts="1719693578">
+ <transform xil_pn:end_ts="1719695037" xil_pn:in_ck="-9033868516707283598" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="230146358404850379" xil_pn:start_ts="1719695033">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Stitch.bld"/>
@@ -208,7 +208,7 @@
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
- <transform xil_pn:end_ts="1719693599" xil_pn:in_ck="-4325218870543059951" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-398923363910175968" xil_pn:start_ts="1719693582">
+ <transform xil_pn:end_ts="1719695054" xil_pn:in_ck="-4325218870543059951" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-398923363910175968" xil_pn:start_ts="1719695037">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -222,7 +222,7 @@
<outfile xil_pn:name="Stitch_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
- <transform xil_pn:end_ts="1719693617" xil_pn:in_ck="-6627939747938971286" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1719693599">
+ <transform xil_pn:end_ts="1719695073" xil_pn:in_ck="-6627939747938971286" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1719695054">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Stitch.ncd"/>
@@ -236,7 +236,7 @@
<outfile xil_pn:name="Stitch_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform>
- <transform xil_pn:end_ts="1719693624" xil_pn:in_ck="4019925351390994" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="4970201210546912173" xil_pn:start_ts="1719693617">
+ <transform xil_pn:end_ts="1719695080" xil_pn:in_ck="4019925351390994" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="4970201210546912173" xil_pn:start_ts="1719695073">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@@ -249,7 +249,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
- <transform xil_pn:end_ts="1719693617" xil_pn:in_ck="-4527387296597967219" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1719693613">
+ <transform xil_pn:end_ts="1719695073" xil_pn:in_ck="-4527387296597967219" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1719695068">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Stitch.twr"/>
diff --git a/stitch_project/stitch/xst/work/work.vdbl b/stitch_project/stitch/xst/work/work.vdbl
index 2e8613a65ed6c328dd1e7f84e9fd21076725dbbc..6cce3b321b17da434d158f14c979fce7a12f418e 100644
GIT binary patch
delta 5550
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diff --git a/stitch_project/stitch/xst/work/work.vdbx b/stitch_project/stitch/xst/work/work.vdbx
index 58c04eb059c6131d23cde7fc8401065f93444cd7..64b0053bf2ae14293e394dd597f4f0fc595ea655 100644
GIT binary patch
delta 28
icmZ3_yq;NDC`X=|je%hS0}wo^l4s^vU$#+r4kG|s9tO++
delta 28
icmZ3_yq;NDC`X=|je%hS0}wo^l4s^%DBLJKhY<i(>joGA
--
GitLab