Stitch Project Status (12/10/2024 - 14:42:15)
Project File: stitch.xise Parser Errors: No Errors
Module Name: Stitch Implementation State: Programming File Generated
Target Device: xc6slx45-2csg324
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
93 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 3,386 54,576 6%  
    Number used as Flip Flops 3,386      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 3,273 27,288 11%  
    Number used as logic 3,021 27,288 11%  
        Number using O6 output only 2,308      
        Number using O5 output only 139      
        Number using O5 and O6 574      
        Number used as ROM 0      
    Number used as Memory 38 6,408 1%  
        Number used as Dual Port RAM 0      
        Number used as Single Port RAM 0      
        Number used as Shift Register 38      
            Number using O6 output only 14      
            Number using O5 output only 0      
            Number using O5 and O6 24      
    Number used exclusively as route-thrus 214      
        Number with same-slice register load 180      
        Number with same-slice carry load 34      
        Number with other load 0      
Number of occupied Slices 1,027 6,822 15%  
Number of MUXCYs used 2,512 13,644 18%  
Number of LUT Flip Flop pairs used 3,539      
    Number with an unused Flip Flop 529 3,539 14%  
    Number with an unused LUT 266 3,539 7%  
    Number of fully used LUT-FF pairs 2,744 3,539 77%  
    Number of unique control sets 39      
    Number of slice register sites lost
        to control set restrictions
104 54,576 1%  
Number of bonded IOBs 22 218 10%  
    Number of LOCed IOBs 22 22 100%  
    IOB Flip Flops 5      
Number of RAMB16BWERs 79 116 68%  
Number of RAMB8BWERs 1 232 1%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 1 16 6%  
    Number used as BUFGs 1      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 8 0%  
Number of ILOGIC2/ISERDES2s 0 376 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 376 0%  
Number of OLOGIC2/OSERDES2s 5 376 1%  
    Number used as OLOGIC2s 5      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 256 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 8 58 13%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 4 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.10      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Dec 10 14:36:05 2024083 Warnings (0 new)52 Infos (4 new)
Translation ReportCurrentTue Dec 10 14:36:29 2024000
Map ReportCurrentTue Dec 10 14:39:12 202409 Warnings (0 new)7 Infos (0 new)
Place and Route ReportCurrentTue Dec 10 14:40:56 2024000
Power Report     
Post-PAR Static Timing ReportCurrentTue Dec 10 14:41:23 2024003 Infos (0 new)
Bitgen ReportCurrentTue Dec 10 14:42:15 202401 Warning (0 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateTue Dec 10 13:48:43 2024
WebTalk Log FileCurrentTue Dec 10 14:42:15 2024

Date Generated: 12/10/2024 - 14:42:16