CHANGE LOG for Xilinx LogiCORE Multiply Accumulator 2.0 Release Date: October 2, 2013 -------------------------------------------------------------------------------- Table of Contents 1. INTRODUCTION 2. DEVICE SUPPORT 3. NEW FEATURE HISTORY 4. RESOLVED ISSUES 5. KNOWN ISSUES & LIMITATIONS 6. TECHNICAL SUPPORT & FEEDBACK 7. CORE RELEASE HISTORY 8. LEGAL DISCLAIMER -------------------------------------------------------------------------------- 1. INTRODUCTION This file contains the change log for all released versions of the Xilinx LogiCORE IP Multiply Accumulator. For the latest core updates, see the product page at: www.xilinx.com/products/ipcenter/Multiply_Accumulator.htm For installation instructions for this release, please go to: www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm For system requirements: www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm 2. DEVICE SUPPORT 2.1. ISE The following device families are supported by the core for this release: All Series 7 devices All Virtex-6 devices All Spartan-6 devices All Virtex-5 devices All Virtex-4 devices All Spartan-3 devices 3. NEW FEATURE HISTORY 3.1 ISE v2.0 - Ongoing new device support. 4. RESOLVED ISSUES 4.1 ISE - N/A 5. KNOWN ISSUES & LIMITATIONS The following are known issues for this core at time of release: 5.1 ISE - When the Multiply Accumulator v2.0 core is configured with an Accumulation Width of 47 or 48 bits, at least one input datatype is set to "Unsigned", and Automatic latency configuration is used, the "Subtract" and "Add/Subtract" Accumulation Modes, and the Bypass control pin, do not function as expected. - In this situation, the core latency is incorrectly calculated, resulting in an invalid configuration within the core. - This will manifest as a mismatch between the netlist and the IP behavioral model. - If reduced pipelining can be tolerated, use the manual latency configuration and force the latency value to "1". - Alternatively, on the IP GUI, any inputs which have an Unsigned type should be increased in width by 1 bit and their type set to Signed. When the IP is instantiated in an HDL design, force the MSB of that input to '0'. - CR671528 - AR52408 - For a comprehensive listing of Known Issues for this core, please see the IP Release Notes Guide, www.xilinx.com/support/documentation/user_guides/xtp025.pdf 6. TECHNICAL SUPPORT & FEEDBACK To obtain technical support, create a WebCase at www.xilinx.com/support. Questions are routed to a team with expertise using this product. Please feel free to leave feedback on this IP under the "Leave Feedback" menu item in Vivado/PlanAhead. Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines. 7. CORE RELEASE HISTORY Date By Version Description ================================================================================ 10/02/2013 Xilinx, Inc. 2.0 ISE 14.7 support and Production support for Series 7 06/19/2012 Xilinx, Inc. 2.0 ISE 14.6 support 03/20/2012 Xilinx, Inc. 2.0 ISE 14.5 support. 12/18/2012 Xilinx, Inc. 2.0 ISE 14.4 and Vivado 2012.4 support 10/16/2012 Xilinx, Inc. 2.0 ISE 14.3 and Vivado 2012.3 support 07/25/2012 Xilinx, Inc. 2.0 ISE 14.2 and Vivado 2012.2 support 04/24/2012 Xilinx, Inc. 2.0 ISE 14.1 and Vivado 2012.1 support 01/11/2012 Xilinx, Inc. 2.0 ISE 13.4 support 10/19/2011 Xilinx, Inc. 2.0 ISE 13.3 support 06/22/2011 Xilinx, Inc. 2.0 ISE 13.2 support, Artix-7 support 03/01/2011 Xilinx, Inc. 2.0 ISE 13.1 support, Virtex-7 and Kintex-7 support 10/29/2010 Xilinx, Inc. 2.0 ISE 7 Series Monthly Snapshot - (O.28) 04/19/2010 Xilinx, Inc. 2.0 ISE 12.1, Virtex-6Q and Spartan-6Q support 12/02/2009 Xilinx, Inc. 2.0 ISE 11.1 Support, Spartan-6L support and Automotive Spartan6 support 09/16/2009 Xilinx, Inc. 2.0 ISE 11.1 Support, Virtex-6L support 04/24/2009 Xilinx, Inc. 2.0 ISE 11.1 Support ================================================================================ 8. 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