Release 14.7 Map P.20131013 (nt64)
Xilinx Mapping Report File for Design 'SoundMaster'
Design Information
------------------
Command Line : map -filter
C:/Users/fpga-programmer/ISEProjects/SpartanSound/iseconfig/filter.filter
-intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0
-register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off
-power off -o SoundMaster_map.ncd SoundMaster.ngd SoundMaster.pcf
Target Device : xc6slx16
Target Package : csg324
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue May 29 13:14:10 2018
Design Summary
--------------
Number of errors: 0
Number of warnings: 2
Slice Logic Utilization:
Number of Slice Registers: 296 out of 18,224 1%
Number used as Flip Flops: 295
Number used as Latches: 1
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 293 out of 9,112 3%
Number used as logic: 220 out of 9,112 2%
Number using O6 output only: 120
Number using O5 output only: 65
Number using O5 and O6: 35
Number used as ROM: 0
Number used as Memory: 58 out of 2,176 2%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 58
Number using O6 output only: 56
Number using O5 output only: 1
Number using O5 and O6: 1
Number used exclusively as route-thrus: 15
Number with same-slice register load: 8
Number with same-slice carry load: 7
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 179 out of 2,278 7%
Number of MUXCYs used: 132 out of 4,556 2%
Number of LUT Flip Flop pairs used: 408
Number with an unused Flip Flop: 131 out of 408 32%
Number with an unused LUT: 115 out of 408 28%
Number of fully used LUT-FF pairs: 162 out of 408 39%
Number of unique control sets: 60
Number of slice register sites lost
to control set restrictions: 317 out of 18,224 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 12 out of 232 5%
Number of LOCed IOBs: 12 out of 12 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 8 out of 32 25%
Number of RAMB8BWERs: 1 out of 64 1%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 0 out of 248 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 248 0%
Number of OLOGIC2/OSERDES2s: 0 out of 248 0%
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 32 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Number of RPM macros: 9
Average Fanout of Non-Clock Nets: 2.92
Peak Memory Usage: 361 MB
Total REAL time to MAP completion: 12 secs
Total CPU time to MAP completion: 12 secs
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:PhysDesignRules:372 - Gated clock. Clock net icon_control0<13> is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
Section 3 - Informational
-------------------------
INFO:LIT:243 - Logical network icon_control0<35> has no load.
INFO:LIT:395 - The above info message is repeated 22 more times for the
following (max. 5 shown):
icon_control0<34>,
icon_control0<33>,
icon_control0<32>,
icon_control0<31>,
icon_control0<30>
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:159 - Net Timing constraints on signal CLK are pushed forward
through input buffer.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
45 block(s) removed
24 block(s) optimized away
30 signal(s) removed
Section 5 - Removed Logic
-------------------------
The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.
To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[10].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[11].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[12].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[13].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[14].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[1].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[2].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[3].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[4].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[5].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[6].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[7].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[8].U_LUT" (ROM)
removed.
Loadless block "U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[9].U_LUT" (ROM)
removed.
Loadless block "U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSR" (ROM) removed.
Loadless block "U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_B"
(ROM) removed.
The signal "icon_control0<35>" is sourceless and has been removed.
The signal "icon_control0<34>" is sourceless and has been removed.
The signal "icon_control0<33>" is sourceless and has been removed.
The signal "icon_control0<32>" is sourceless and has been removed.
The signal "icon_control0<31>" is sourceless and has been removed.
The signal "icon_control0<30>" is sourceless and has been removed.
The signal "icon_control0<29>" is sourceless and has been removed.
The signal "icon_control0<28>" is sourceless and has been removed.
The signal "icon_control0<27>" is sourceless and has been removed.
The signal "icon_control0<26>" is sourceless and has been removed.
The signal "icon_control0<25>" is sourceless and has been removed.
The signal "icon_control0<24>" is sourceless and has been removed.
The signal "icon_control0<23>" is sourceless and has been removed.
The signal "icon_control0<22>" is sourceless and has been removed.
The signal "icon_control0<21>" is sourceless and has been removed.
The signal "icon_control0<18>" is sourceless and has been removed.
The signal "icon_control0<17>" is sourceless and has been removed.
The signal "icon_control0<16>" is sourceless and has been removed.
The signal "icon_control0<15>" is sourceless and has been removed.
The signal "icon_control0<11>" is sourceless and has been removed.
The signal "icon_control0<10>" is sourceless and has been removed.
The signal "icon_control0<7>" is sourceless and has been removed.
The signal "U_icon_pro/U0/U_ICON/iCOMMAND_SEL<14>" is sourceless and has been
removed.
Sourceless block "U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[14].U_HCE"
(ROM) removed.
Sourceless block "U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[14].U_LCE"
(ROM) removed.
The signal "U_icon_pro/U0/U_ICON/iCOMMAND_SEL<13>" is sourceless and has been
removed.
Sourceless block "U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[13].U_HCE"
(ROM) removed.
Sourceless block "U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[13].U_LCE"
(ROM) removed.
The signal "U_icon_pro/U0/U_ICON/iCOMMAND_SEL<12>" is sourceless and has been
removed.
Sourceless block "U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[12].U_HCE"
(ROM) removed.
Sourceless block "U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[12].U_LCE"
(ROM) removed.
The signal "U_icon_pro/U0/U_ICON/iCOMMAND_SEL<11>" is sourceless and has been
removed.
Sourceless block "U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[11].U_HCE"
(ROM) removed.
Sourceless block "U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[11].U_LCE"
(ROM) removed.
The signal "U_icon_pro/U0/U_ICON/iCOMMAND_SEL<7>" is sourceless and has been
removed.
Sourceless block "U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[7].U_HCE" (ROM)
removed.
Sourceless block "U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[7].U_LCE" (ROM)
removed.
The signal "U_icon_pro/U0/U_ICON/iCOMMAND_SEL<6>" is sourceless and has been
removed.
Sourceless block "U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[6].U_HCE" (ROM)
removed.
Sourceless block "U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[6].U_LCE" (ROM)
removed.
The signal "U_icon_pro/U0/U_ICON/iCOMMAND_SEL<3>" is sourceless and has been
removed.
Sourceless block "U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[3].U_HCE" (ROM)
removed.
Sourceless block "U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[3].U_LCE" (ROM)
removed.
The signal
"U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GANDX.U_match/I
_CS_GANDX.U_CS_GANDX_SRL/I_S6.U_CS_GANDX_SRL_S6/U_CS_GAND_SRL_S6/I_USE_RPM_NE0.U
_GAND_SRL_SET/SRL_Q_O" is sourceless and has been removed.
Unused block "U_icon_pro/U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[11].U_LUT" (ROM)
removed.
Unused block "U_icon_pro/U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[12].U_LUT" (ROM)
removed.
Unused block "U_icon_pro/U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[13].U_LUT" (ROM)
removed.
Unused block "U_icon_pro/U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[14].U_LUT" (ROM)
removed.
Unused block "U_icon_pro/U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[3].U_LUT" (ROM)
removed.
Unused block "U_icon_pro/U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[6].U_LUT" (ROM)
removed.
Unused block "U_icon_pro/U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[7].U_LUT" (ROM)
removed.
Unused block "U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[10].U_HCE" (ROM)
removed.
Unused block "U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_HCE" (ROM)
removed.
Unused block "U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_HCE" (ROM)
removed.
Unused block "U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[2].U_HCE" (ROM)
removed.
Unused block "U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[4].U_HCE" (ROM)
removed.
Unused block "U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[5].U_HCE" (ROM)
removed.
Unused block "U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[8].U_HCE" (ROM)
removed.
Unused block "U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_HCE" (ROM)
removed.
Optimized Block(s):
TYPE BLOCK
GND BufA/XST_GND
VCC BufA/XST_VCC
GND BufB/XST_GND
VCC BufB/XST_VCC
GND U_icon_pro/XST_GND
VCC U_icon_pro/XST_VCC
GND
U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_CS_GA
ND.U_CS_GAND_SRL/I_S6.U_CS_GAND_SRL_S6/I_USE_RPM_NE0.U_GAND_SRL_SET/I_PARTIAL_SL
ICE.U_GAND_SRL_SLICE/XST_GND
VCC
U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_CS_GA
ND.U_CS_GAND_SRL/I_S6.U_CS_GAND_SRL_S6/I_USE_RPM_NE0.U_GAND_SRL_SET/I_PARTIAL_SL
ICE.U_GAND_SRL_SLICE/XST_VCC
VCC
U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_CS_GA
ND.U_CS_GAND_SRL/I_S6.U_CS_GAND_SRL_S6/I_USE_RPM_NE0.U_GAND_SRL_SET/XST_VCC
GND
U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_CS_G
AND.U_CS_GAND_SRL/I_S6.U_CS_GAND_SRL_S6/I_USE_RPM_NE0.U_GAND_SRL_SET/I_PARTIAL_S
LICE.U_GAND_SRL_SLICE/XST_GND
VCC
U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_CS_G
AND.U_CS_GAND_SRL/I_S6.U_CS_GAND_SRL_S6/I_USE_RPM_NE0.U_GAND_SRL_SET/I_PARTIAL_S
LICE.U_GAND_SRL_SLICE/XST_VCC
VCC
U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_CS_G
AND.U_CS_GAND_SRL/I_S6.U_CS_GAND_SRL_S6/I_USE_RPM_NE0.U_GAND_SRL_SET/XST_VCC
GND
U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_CS_G
AND.U_CS_GAND_SRL/I_S6.U_CS_GAND_SRL_S6/I_USE_RPM_NE0.U_GAND_SRL_SET/I_PARTIAL_S
LICE.U_GAND_SRL_SLICE/XST_GND
VCC
U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_CS_G
AND.U_CS_GAND_SRL/I_S6.U_CS_GAND_SRL_S6/I_USE_RPM_NE0.U_GAND_SRL_SET/I_PARTIAL_S
LICE.U_GAND_SRL_SLICE/XST_VCC
VCC
U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_CS_G
AND.U_CS_GAND_SRL/I_S6.U_CS_GAND_SRL_S6/I_USE_RPM_NE0.U_GAND_SRL_SET/XST_VCC
LUT4 U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[6].I_STAT.U_STAT
optimized to 0
GND
U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GANDX.U_match/
I_CS_GANDX.U_CS_GANDX_SRL/I_S6.U_CS_GANDX_SRL_S6/U_CS_GAND_SRL_S6/I_USE_RPM_NE0.
U_GAND_SRL_SET/I_WHOLE_SLICE.G_SLICE_IDX[0].U_GAND_SRL_SLICE/XST_GND
VCC
U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GANDX.U_match/
I_CS_GANDX.U_CS_GANDX_SRL/I_S6.U_CS_GANDX_SRL_S6/U_CS_GAND_SRL_S6/I_USE_RPM_NE0.
U_GAND_SRL_SET/I_WHOLE_SLICE.G_SLICE_IDX[0].U_GAND_SRL_SLICE/XST_VCC
GND U_ila_pro_0/XST_GND
VCC U_ila_pro_0/XST_VCC
GND XST_GND
VCC XST_VCC
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| CLK | IOB | INPUT | LVCMOS25 | | | | | | |
| LED0 | IOB | OUTPUT | LVTTL | | 8 | FAST | | | |
| LED1 | IOB | OUTPUT | LVTTL | | 8 | FAST | | | |
| LED2 | IOB | OUTPUT | LVTTL | | 8 | FAST | | | |
| LED3 | IOB | OUTPUT | LVTTL | | 8 | FAST | | | |
| LED4 | IOB | OUTPUT | LVTTL | | 8 | FAST | | | |
| LED5 | IOB | OUTPUT | LVTTL | | 8 | FAST | | | |
| LED6 | IOB | OUTPUT | LVTTL | | 8 | FAST | | | |
| LED7 | IOB | OUTPUT | LVTTL | | 8 | FAST | | | |
| RXN | IOB | INPUT | LVTTL | | | | | | |
| TXN | IOB | OUTPUT | LVTTL | | 8 | FAST | | | |
| VOUTN | IOB | OUTPUT | LVTTL | | 8 | FAST | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_CS_GAND
.U_CS_GAND_SRL/I_S6.U_CS_GAND_SRL_S6/I_USE_RPM_NE0.U_GAND_SRL_SET/MSET
U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_CS_GAN
D.U_CS_GAND_SRL/I_S6.U_CS_GAND_SRL_S6/I_USE_RPM_NE0.U_GAND_SRL_SET/MSET
U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_CS_GAN
D.U_CS_GAND_SRL/I_S6.U_CS_GAND_SRL_S6/I_USE_RPM_NE0.U_GAND_SRL_SET/MSET
U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL_I_SRLT_NE_1.U_CDONE_MSET
U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL_I_SRLT_NE_1.U_CMPRESET_MSET
U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL_I_SRLT_NE_1.U_NS0_MSET
U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL_I_SRLT_NE_1.U_NS1_MSET
U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL_I_SRLT_NE_1.U_SCRST_MSET
U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GANDX.U_match/I_
CS_GANDX.U_CS_GANDX_SRL/I_S6.U_CS_GANDX_SRL_S6/U_CS_GAND_SRL_S6/I_USE_RPM_NE0.U_
GAND_SRL_SET/MSET
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.