SoundMaster Project Status (05/29/2018 - 13:15:12)
Project File: SpartanSound.xise Parser Errors: No Errors
Module Name: SoundMaster Implementation State: Programming File Generated
Target Device: xc6slx16-2csg324
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
7 Warnings (4 new, 0 filtered)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 296 18,224 1%  
    Number used as Flip Flops 295      
    Number used as Latches 1      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 293 9,112 3%  
    Number used as logic 220 9,112 2%  
        Number using O6 output only 120      
        Number using O5 output only 65      
        Number using O5 and O6 35      
        Number used as ROM 0      
    Number used as Memory 58 2,176 2%  
        Number used as Dual Port RAM 0      
        Number used as Single Port RAM 0      
        Number used as Shift Register 58      
            Number using O6 output only 56      
            Number using O5 output only 1      
            Number using O5 and O6 1      
    Number used exclusively as route-thrus 15      
        Number with same-slice register load 8      
        Number with same-slice carry load 7      
        Number with other load 0      
Number of occupied Slices 179 2,278 7%  
Number of MUXCYs used 132 4,556 2%  
Number of LUT Flip Flop pairs used 408      
    Number with an unused Flip Flop 131 408 32%  
    Number with an unused LUT 115 408 28%  
    Number of fully used LUT-FF pairs 162 408 39%  
    Number of unique control sets 60      
    Number of slice register sites lost
        to control set restrictions
317 18,224 1%  
Number of bonded IOBs 12 232 5%  
    Number of LOCed IOBs 12 12 100%  
Number of RAMB16BWERs 8 32 25%  
Number of RAMB8BWERs 1 64 1%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 2 16 12%  
    Number used as BUFGs 2      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 248 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 248 0%  
Number of OLOGIC2/OSERDES2s 0 248 0%  
Number of BSCANs 1 4 25%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 32 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Number of RPM macros 9      
Average Fanout of Non-Clock Nets 2.92      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue May 29 12:53:40 201803 Warnings (0 new, 0 filtered)3 Infos (0 new, 0 filtered)
Translation ReportCurrentTue May 29 13:14:06 2018001 Info (0 new, 0 filtered)
Map ReportCurrentTue May 29 13:14:23 201802 Warnings (2 new, 0 filtered)8 Infos (2 new, 0 filtered)
Place and Route ReportCurrentTue May 29 13:14:37 2018001 Info (1 new, 0 filtered)
Power Report     
Post-PAR Static Timing ReportCurrentTue May 29 13:14:46 2018003 Infos (0 new, 0 filtered)
Bitgen ReportCurrentTue May 29 13:15:02 201802 Warnings (2 new, 0 filtered)1 Info (1 new, 0 filtered)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentTue May 29 13:15:02 2018
WebTalk Log FileCurrentTue May 29 13:15:11 2018

Date Generated: 05/29/2018 - 13:15:12