Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx16
Project ID (random number) 2570778275844fbc84d0a0c1e5e9847f.B998B51339B749A49736A6F4F9775C0E.5 Target Package: csg324
Registration ID 211536092_0_0_031 Target Speed: -2
Date Generated 2018-05-29T13:15:02 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name AMD Athlon(tm) 64 X2 Dual Core Processor 6000+ CPU Speed 3000 MHz
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name AMD Athlon(tm) 64 X2 Dual Core Processor 6000+ CPU Speed 3000 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=4
  • 11-bit adder=1
  • 5-bit adder=2
  • 9-bit adder=1
Counters=2
  • 13-bit up counter=1
  • 14-bit up counter=1
Registers=64
  • Flip-Flops=64
Xors=5
  • 1-bit xor2=5
MiscellaneousStatistics
  • AGG_BONDED_IO=12
  • AGG_IO=12
  • AGG_LOCED_IO=12
  • AGG_SLICE=179
  • NUM_BONDED_IOB=12
  • NUM_BSCAN=1
  • NUM_BSFULL=162
  • NUM_BSLUTONLY=131
  • NUM_BSREGONLY=115
  • NUM_BSUSED=408
  • NUM_BUFG=2
  • NUM_LOCED_IOB=12
  • NUM_LOGIC_O5ANDO6=35
  • NUM_LOGIC_O5ONLY=65
  • NUM_LOGIC_O6ONLY=120
  • NUM_LUT_RT_DRIVES_CARRY4=7
  • NUM_LUT_RT_DRIVES_FLOP=8
  • NUM_LUT_RT_EXO5=8
  • NUM_LUT_RT_EXO6=7
  • NUM_LUT_RT_O5=5
  • NUM_LUT_RT_O6=65
  • NUM_RAMB16BWER=8
  • NUM_RAMB8BWER=1
  • NUM_RPM=9
  • NUM_SLICEL=34
  • NUM_SLICEM=30
  • NUM_SLICEX=115
  • NUM_SLICE_CARRY4=33
  • NUM_SLICE_CONTROLSET=60
  • NUM_SLICE_CYINIT=412
  • NUM_SLICE_F7MUX=12
  • NUM_SLICE_F8MUX=2
  • NUM_SLICE_FF=295
  • NUM_SLICE_LATCH=1
  • NUM_SLICE_UNUSEDCTRL=30
  • NUM_SRL_O5ANDO6=1
  • NUM_SRL_O5ONLY=1
  • NUM_SRL_O6ONLY=56
  • NUM_UNUSABLE_FF_BELS=317
  • Xilinx Core blk_mem_gen_v7_3, Xilinx CORE Generator 14.7=2
  • Xilinx Core chipscope_icon_v1_06_a, Xilinx CORE Generator 14.7=1
  • Xilinx Core chipscope_ila_v1_05_a, Xilinx CORE Generator 14.7=1
NetStatistics
  • NumNets_Active=527
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=18
  • NumNodesOfType_Active_BOUNCEIN=104
  • NumNodesOfType_Active_BUFGOUT=2
  • NumNodesOfType_Active_BUFHINP2OUT=7
  • NumNodesOfType_Active_CLKPIN=149
  • NumNodesOfType_Active_CLKPINFEED=11
  • NumNodesOfType_Active_CNTRLPIN=140
  • NumNodesOfType_Active_DOUBLE=629
  • NumNodesOfType_Active_GENERIC=13
  • NumNodesOfType_Active_GLOBAL=53
  • NumNodesOfType_Active_INPUT=239
  • NumNodesOfType_Active_IOBIN2OUT=11
  • NumNodesOfType_Active_IOBOUTPUT=11
  • NumNodesOfType_Active_LUTINPUT=855
  • NumNodesOfType_Active_OUTBOUND=523
  • NumNodesOfType_Active_OUTPUT=536
  • NumNodesOfType_Active_PADINPUT=10
  • NumNodesOfType_Active_PADOUTPUT=2
  • NumNodesOfType_Active_PINBOUNCE=461
  • NumNodesOfType_Active_PINFEED=1262
  • NumNodesOfType_Active_QUAD=357
  • NumNodesOfType_Active_REGINPUT=157
  • NumNodesOfType_Active_SINGLE=958
  • NumNodesOfType_Gnd_BOUNCEIN=111
  • NumNodesOfType_Gnd_DOUBLE=2
  • NumNodesOfType_Gnd_HGNDOUT=42
  • NumNodesOfType_Gnd_INPUT=770
  • NumNodesOfType_Gnd_LUTINPUT=13
  • NumNodesOfType_Gnd_OUTBOUND=4
  • NumNodesOfType_Gnd_OUTPUT=4
  • NumNodesOfType_Gnd_PINBOUNCE=209
  • NumNodesOfType_Gnd_PINFEED=711
  • NumNodesOfType_Gnd_REGINPUT=17
  • NumNodesOfType_Gnd_SINGLE=3
  • NumNodesOfType_Vcc_CNTRLPIN=3
  • NumNodesOfType_Vcc_HVCCOUT=79
  • NumNodesOfType_Vcc_INPUT=44
  • NumNodesOfType_Vcc_KVCCOUT=37
  • NumNodesOfType_Vcc_LUTINPUT=264
  • NumNodesOfType_Vcc_PINBOUNCE=11
  • NumNodesOfType_Vcc_PINFEED=304
  • NumNodesOfType_Vcc_REGINPUT=4
SiteStatistics
  • BUFG-BUFGMUX=2
  • IOB-IOBM=1
  • IOB-IOBS=11
  • SLICEL-SLICEM=10
  • SLICEX-SLICEL=26
  • SLICEX-SLICEM=28
SiteSummary
  • BSCAN=1
  • BSCAN_BSCAN=1
  • BUFG=2
  • BUFG_BUFG=2
  • CARRY4=33
  • FF_SR=24
  • HARD0=3
  • HARD1=10
  • IOB=12
  • IOB_IMUX=2
  • IOB_INBUF=2
  • IOB_OUTBUF=10
  • LUT5=113
  • LUT6=227
  • LUT_OR_MEM5=2
  • LUT_OR_MEM6=57
  • PAD=12
  • RAMB16BWER=8
  • RAMB16BWER_RAMB16BWER=8
  • RAMB8BWER=1
  • RAMB8BWER_RAMB8BWER=1
  • REG_SR=272
  • SELMUX2_1=14
  • SLICEL=34
  • SLICEM=30
  • SLICEX=115
 
Configuration Data
BSCAN_BSCAN
  • JTAG_CHAIN=[1:1]
  • JTAG_TEST=[0:1]
FF_SR
  • CK=[CK:24] [CK_INV:0]
  • SRINIT=[SRINIT0:23] [SRINIT1:1]
  • SYNC_ATTR=[ASYNC:14] [SYNC:10]
IOB_OUTBUF
  • DRIVEATTRBOX=[8:10]
  • SLEW=[FAST:10]
  • SUSPEND=[3STATE:10]
LUT_OR_MEM5
  • CLK=[CLK:2] [CLK_INV:0]
  • LUT_OR_MEM=[RAM:2]
  • RAMMODE=[SRL16:2]
LUT_OR_MEM6
  • CLK=[CLK:57] [CLK_INV:0]
  • LUT_OR_MEM=[RAM:57]
  • RAMMODE=[SRL16:28] [SRL32:29]
RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:8]
  • CLKB=[CLKB_INV:0] [CLKB:8]
  • ENA=[ENA_INV:0] [ENA:8]
  • ENB=[ENB_INV:0] [ENB:8]
  • REGCEA=[REGCEA_INV:0] [REGCEA:8]
  • REGCEB=[REGCEB_INV:0] [REGCEB:8]
  • RSTA=[RSTA:8] [RSTA_INV:0]
  • RSTB=[RSTB:8] [RSTB_INV:0]
  • WEA0=[WEA0:8] [WEA0_INV:0]
  • WEA1=[WEA1:8] [WEA1_INV:0]
  • WEA2=[WEA2:8] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:8]
  • WEB0=[WEB0:8] [WEB0_INV:0]
  • WEB1=[WEB1:8] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:8]
  • WEB3=[WEB3:8] [WEB3_INV:0]
RAMB16BWER_RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:8]
  • CLKB=[CLKB_INV:0] [CLKB:8]
  • DATA_WIDTH_A=[2:8]
  • DATA_WIDTH_B=[2:8]
  • DOA_REG=[0:8]
  • DOB_REG=[0:8]
  • ENA=[ENA_INV:0] [ENA:8]
  • ENB=[ENB_INV:0] [ENB:8]
  • EN_RSTRAM_A=[FALSE:8]
  • EN_RSTRAM_B=[FALSE:8]
  • RAM_MODE=[TDP:8]
  • REGCEA=[REGCEA_INV:0] [REGCEA:8]
  • REGCEB=[REGCEB_INV:0] [REGCEB:8]
  • RSTA=[RSTA:8] [RSTA_INV:0]
  • RSTB=[RSTB:8] [RSTB_INV:0]
  • RSTTYPE=[SYNC:8]
  • RST_PRIORITY_A=[CE:8]
  • RST_PRIORITY_B=[CE:8]
  • WEA0=[WEA0:8] [WEA0_INV:0]
  • WEA1=[WEA1:8] [WEA1_INV:0]
  • WEA2=[WEA2:8] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:8]
  • WEB0=[WEB0:8] [WEB0_INV:0]
  • WEB1=[WEB1:8] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:8]
  • WEB3=[WEB3:8] [WEB3_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:8]
  • WRITE_MODE_B=[WRITE_FIRST:8]
RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:1] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:1]
  • ENAWREN=[ENAWREN:1] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:1] [RSTBRST_INV:0]
  • WEAWEL0=[WEAWEL0:1] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:1]
  • WEBWEU0=[WEBWEU0:1] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:1] [WEBWEU1_INV:0]
RAMB8BWER_RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:1] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:1]
  • DATA_WIDTH_A=[9:1]
  • DATA_WIDTH_B=[9:1]
  • DOA_REG=[0:1]
  • DOB_REG=[0:1]
  • ENAWREN=[ENAWREN:1] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:1]
  • EN_RSTRAM_A=[FALSE:1]
  • EN_RSTRAM_B=[FALSE:1]
  • RAM_MODE=[TDP:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:1] [RSTBRST_INV:0]
  • RSTTYPE=[SYNC:1]
  • RST_PRIORITY_A=[CE:1]
  • RST_PRIORITY_B=[CE:1]
  • WEAWEL0=[WEAWEL0:1] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:1]
  • WEBWEU0=[WEBWEU0:1] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:1] [WEBWEU1_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:1]
  • WRITE_MODE_B=[WRITE_FIRST:1]
REG_SR
  • CK=[CK:271] [CK_INV:1]
  • LATCH_OR_FF=[FF:271] [LATCH:1]
  • SRINIT=[SRINIT0:251] [SRINIT1:21]
  • SYNC_ATTR=[ASYNC:128] [SYNC:144]
SLICEL
  • CLK=[CLK:32] [CLK_INV:0]
SLICEM
  • CLK=[CLK:30] [CLK_INV:0]
SLICEX
  • CLK=[CLK:86] [CLK_INV:1]
 
Pin Data
BSCAN
  • DRCK=1
  • SEL=1
  • SHIFT=1
  • TDI=1
  • TDO=1
  • UPDATE=1
BSCAN_BSCAN
  • DRCK=1
  • SEL=1
  • SHIFT=1
  • TDI=1
  • TDO=1
  • UPDATE=1
BUFG
  • I0=2
  • O=2
BUFG_BUFG
  • I0=2
  • O=2
CARRY4
  • CIN=20
  • CO0=4
  • CO3=21
  • CYINIT=13
  • DI0=28
  • DI1=21
  • DI2=21
  • DI3=21
  • O0=25
  • O1=24
  • O2=17
  • O3=17
  • S0=33
  • S1=28
  • S2=21
  • S3=21
FF_SR
  • CE=4
  • CK=24
  • D=24
  • Q=24
  • SR=10
HARD0
  • 0=3
HARD1
  • 1=10
IOB
  • I=2
  • O=10
  • PAD=12
IOB_IMUX
  • I=2
  • OUT=2
IOB_INBUF
  • OUT=2
  • PAD=2
IOB_OUTBUF
  • IN=10
  • OUT=10
LUT5
  • A1=11
  • A2=19
  • A3=26
  • A4=22
  • A5=36
  • O5=113
LUT6
  • A1=29
  • A2=47
  • A3=105
  • A4=212
  • A5=140
  • A6=214
  • O6=227
LUT_OR_MEM5
  • A1=2
  • A2=2
  • A3=2
  • A4=2
  • A5=2
  • CLK=2
  • DI1=2
  • O5=2
  • WE=2
LUT_OR_MEM6
  • A1=57
  • A2=57
  • A3=57
  • A4=57
  • A5=57
  • A6=57
  • CLK=57
  • DI1=29
  • DI2=28
  • MC31=49
  • O6=57
  • WE=57
PAD
  • PAD=12
RAMB16BWER
  • ADDRA0=8
  • ADDRA1=8
  • ADDRA10=8
  • ADDRA11=8
  • ADDRA12=8
  • ADDRA13=8
  • ADDRA2=8
  • ADDRA3=8
  • ADDRA4=8
  • ADDRA5=8
  • ADDRA6=8
  • ADDRA7=8
  • ADDRA8=8
  • ADDRA9=8
  • ADDRB0=8
  • ADDRB1=8
  • ADDRB10=8
  • ADDRB11=8
  • ADDRB12=8
  • ADDRB13=8
  • ADDRB2=8
  • ADDRB3=8
  • ADDRB4=8
  • ADDRB5=8
  • ADDRB6=8
  • ADDRB7=8
  • ADDRB8=8
  • ADDRB9=8
  • CLKA=8
  • CLKB=8
  • DIA0=8
  • DIA1=8
  • DIA10=8
  • DIA11=8
  • DIA12=8
  • DIA13=8
  • DIA14=8
  • DIA15=8
  • DIA16=8
  • DIA17=8
  • DIA18=8
  • DIA19=8
  • DIA2=8
  • DIA20=8
  • DIA21=8
  • DIA22=8
  • DIA23=8
  • DIA24=8
  • DIA25=8
  • DIA26=8
  • DIA27=8
  • DIA28=8
  • DIA29=8
  • DIA3=8
  • DIA30=8
  • DIA31=8
  • DIA4=8
  • DIA5=8
  • DIA6=8
  • DIA7=8
  • DIA8=8
  • DIA9=8
  • DIB0=8
  • DIB1=8
  • DIB10=8
  • DIB11=8
  • DIB12=8
  • DIB13=8
  • DIB14=8
  • DIB15=8
  • DIB16=8
  • DIB17=8
  • DIB18=8
  • DIB19=8
  • DIB2=8
  • DIB20=8
  • DIB21=8
  • DIB22=8
  • DIB23=8
  • DIB24=8
  • DIB25=8
  • DIB26=8
  • DIB27=8
  • DIB28=8
  • DIB29=8
  • DIB3=8
  • DIB30=8
  • DIB31=8
  • DIB4=8
  • DIB5=8
  • DIB6=8
  • DIB7=8
  • DIB8=8
  • DIB9=8
  • DIPA0=8
  • DIPA1=8
  • DIPA2=8
  • DIPA3=8
  • DIPB0=8
  • DIPB1=8
  • DIPB2=8
  • DIPB3=8
  • DOA0=8
  • DOA1=8
  • ENA=8
  • ENB=8
  • REGCEA=8
  • REGCEB=8
  • RSTA=8
  • RSTB=8
  • WEA0=8
  • WEA1=8
  • WEA2=8
  • WEA3=8
  • WEB0=8
  • WEB1=8
  • WEB2=8
  • WEB3=8
RAMB16BWER_RAMB16BWER
  • ADDRA0=8
  • ADDRA1=8
  • ADDRA10=8
  • ADDRA11=8
  • ADDRA12=8
  • ADDRA13=8
  • ADDRA2=8
  • ADDRA3=8
  • ADDRA4=8
  • ADDRA5=8
  • ADDRA6=8
  • ADDRA7=8
  • ADDRA8=8
  • ADDRA9=8
  • ADDRB0=8
  • ADDRB1=8
  • ADDRB10=8
  • ADDRB11=8
  • ADDRB12=8
  • ADDRB13=8
  • ADDRB2=8
  • ADDRB3=8
  • ADDRB4=8
  • ADDRB5=8
  • ADDRB6=8
  • ADDRB7=8
  • ADDRB8=8
  • ADDRB9=8
  • CLKA=8
  • CLKB=8
  • DIA0=8
  • DIA1=8
  • DIA10=8
  • DIA11=8
  • DIA12=8
  • DIA13=8
  • DIA14=8
  • DIA15=8
  • DIA16=8
  • DIA17=8
  • DIA18=8
  • DIA19=8
  • DIA2=8
  • DIA20=8
  • DIA21=8
  • DIA22=8
  • DIA23=8
  • DIA24=8
  • DIA25=8
  • DIA26=8
  • DIA27=8
  • DIA28=8
  • DIA29=8
  • DIA3=8
  • DIA30=8
  • DIA31=8
  • DIA4=8
  • DIA5=8
  • DIA6=8
  • DIA7=8
  • DIA8=8
  • DIA9=8
  • DIB0=8
  • DIB1=8
  • DIB10=8
  • DIB11=8
  • DIB12=8
  • DIB13=8
  • DIB14=8
  • DIB15=8
  • DIB16=8
  • DIB17=8
  • DIB18=8
  • DIB19=8
  • DIB2=8
  • DIB20=8
  • DIB21=8
  • DIB22=8
  • DIB23=8
  • DIB24=8
  • DIB25=8
  • DIB26=8
  • DIB27=8
  • DIB28=8
  • DIB29=8
  • DIB3=8
  • DIB30=8
  • DIB31=8
  • DIB4=8
  • DIB5=8
  • DIB6=8
  • DIB7=8
  • DIB8=8
  • DIB9=8
  • DIPA0=8
  • DIPA1=8
  • DIPA2=8
  • DIPA3=8
  • DIPB0=8
  • DIPB1=8
  • DIPB2=8
  • DIPB3=8
  • DOA0=8
  • DOA1=8
  • ENA=8
  • ENB=8
  • REGCEA=8
  • REGCEB=8
  • RSTA=8
  • RSTB=8
  • WEA0=8
  • WEA1=8
  • WEA2=8
  • WEA3=8
  • WEB0=8
  • WEB1=8
  • WEB2=8
  • WEB3=8
RAMB8BWER
  • ADDRAWRADDR0=1
  • ADDRAWRADDR1=1
  • ADDRAWRADDR10=1
  • ADDRAWRADDR11=1
  • ADDRAWRADDR12=1
  • ADDRAWRADDR2=1
  • ADDRAWRADDR3=1
  • ADDRAWRADDR4=1
  • ADDRAWRADDR5=1
  • ADDRAWRADDR6=1
  • ADDRAWRADDR7=1
  • ADDRAWRADDR8=1
  • ADDRAWRADDR9=1
  • ADDRBRDADDR0=1
  • ADDRBRDADDR1=1
  • ADDRBRDADDR10=1
  • ADDRBRDADDR11=1
  • ADDRBRDADDR12=1
  • ADDRBRDADDR2=1
  • ADDRBRDADDR3=1
  • ADDRBRDADDR4=1
  • ADDRBRDADDR5=1
  • ADDRBRDADDR6=1
  • ADDRBRDADDR7=1
  • ADDRBRDADDR8=1
  • ADDRBRDADDR9=1
  • CLKAWRCLK=1
  • CLKBRDCLK=1
  • DIADI0=1
  • DIADI1=1
  • DIADI10=1
  • DIADI11=1
  • DIADI12=1
  • DIADI13=1
  • DIADI14=1
  • DIADI15=1
  • DIADI2=1
  • DIADI3=1
  • DIADI4=1
  • DIADI5=1
  • DIADI6=1
  • DIADI7=1
  • DIADI8=1
  • DIADI9=1
  • DIBDI0=1
  • DIBDI1=1
  • DIBDI10=1
  • DIBDI11=1
  • DIBDI12=1
  • DIBDI13=1
  • DIBDI14=1
  • DIBDI15=1
  • DIBDI2=1
  • DIBDI3=1
  • DIBDI4=1
  • DIBDI5=1
  • DIBDI6=1
  • DIBDI7=1
  • DIBDI8=1
  • DIBDI9=1
  • DIPADIP0=1
  • DIPADIP1=1
  • DIPBDIP0=1
  • DIPBDIP1=1
  • DOADO0=1
  • DOADO1=1
  • DOADO2=1
  • DOADO3=1
  • ENAWREN=1
  • ENBRDEN=1
  • REGCEA=1
  • REGCEBREGCE=1
  • RSTA=1
  • RSTBRST=1
  • WEAWEL0=1
  • WEAWEL1=1
  • WEBWEU0=1
  • WEBWEU1=1
RAMB8BWER_RAMB8BWER
  • ADDRAWRADDR0=1
  • ADDRAWRADDR1=1
  • ADDRAWRADDR10=1
  • ADDRAWRADDR11=1
  • ADDRAWRADDR12=1
  • ADDRAWRADDR2=1
  • ADDRAWRADDR3=1
  • ADDRAWRADDR4=1
  • ADDRAWRADDR5=1
  • ADDRAWRADDR6=1
  • ADDRAWRADDR7=1
  • ADDRAWRADDR8=1
  • ADDRAWRADDR9=1
  • ADDRBRDADDR0=1
  • ADDRBRDADDR1=1
  • ADDRBRDADDR10=1
  • ADDRBRDADDR11=1
  • ADDRBRDADDR12=1
  • ADDRBRDADDR2=1
  • ADDRBRDADDR3=1
  • ADDRBRDADDR4=1
  • ADDRBRDADDR5=1
  • ADDRBRDADDR6=1
  • ADDRBRDADDR7=1
  • ADDRBRDADDR8=1
  • ADDRBRDADDR9=1
  • CLKAWRCLK=1
  • CLKBRDCLK=1
  • DIADI0=1
  • DIADI1=1
  • DIADI10=1
  • DIADI11=1
  • DIADI12=1
  • DIADI13=1
  • DIADI14=1
  • DIADI15=1
  • DIADI2=1
  • DIADI3=1
  • DIADI4=1
  • DIADI5=1
  • DIADI6=1
  • DIADI7=1
  • DIADI8=1
  • DIADI9=1
  • DIBDI0=1
  • DIBDI1=1
  • DIBDI10=1
  • DIBDI11=1
  • DIBDI12=1
  • DIBDI13=1
  • DIBDI14=1
  • DIBDI15=1
  • DIBDI2=1
  • DIBDI3=1
  • DIBDI4=1
  • DIBDI5=1
  • DIBDI6=1
  • DIBDI7=1
  • DIBDI8=1
  • DIBDI9=1
  • DIPADIP0=1
  • DIPADIP1=1
  • DIPBDIP0=1
  • DIPBDIP1=1
  • DOADO0=1
  • DOADO1=1
  • DOADO2=1
  • DOADO3=1
  • ENAWREN=1
  • ENBRDEN=1
  • REGCEA=1
  • REGCEBREGCE=1
  • RSTA=1
  • RSTBRST=1
  • WEAWEL0=1
  • WEAWEL1=1
  • WEBWEU0=1
  • WEBWEU1=1
REG_SR
  • CE=78
  • CK=272
  • D=272
  • Q=272
  • SR=175
SELMUX2_1
  • 0=14
  • 1=14
  • OUT=14
  • S0=14
SLICEL
  • A=1
  • A1=1
  • A2=1
  • A3=4
  • A4=28
  • A5=4
  • A6=27
  • AQ=31
  • AX=2
  • B=4
  • B1=1
  • B2=1
  • B3=4
  • B4=27
  • B5=5
  • B6=20
  • BQ=25
  • BX=2
  • C=1
  • C1=4
  • C2=5
  • C3=7
  • C4=22
  • C5=8
  • C6=23
  • CE=13
  • CIN=20
  • CLK=32
  • CMUX=3
  • COUT=16
  • CQ=19
  • CX=7
  • D=1
  • D1=3
  • D2=5
  • D3=8
  • D4=23
  • D5=8
  • D6=23
  • DMUX=1
  • DQ=17
  • DX=2
  • SR=24
SLICEM
  • A=17
  • A1=27
  • A2=27
  • A3=27
  • A4=27
  • A5=27
  • A6=27
  • AI=17
  • AMUX=4
  • AQ=1
  • AX=10
  • B=1
  • B1=12
  • B2=12
  • B3=12
  • B4=12
  • B5=12
  • B6=12
  • BI=2
  • BMUX=2
  • BQ=3
  • BX=9
  • C=3
  • C1=12
  • C2=12
  • C3=12
  • C4=12
  • C5=12
  • C6=11
  • CE=30
  • CI=4
  • CLK=30
  • CMUX=1
  • COUT=4
  • CQ=3
  • CX=8
  • D=1
  • D1=7
  • D2=7
  • D3=7
  • D4=7
  • D5=7
  • D6=7
  • DI=5
  • DMUX=24
  • DQ=1
  • DX=7
SLICEX
  • A=28
  • A1=13
  • A2=17
  • A3=27
  • A4=40
  • A5=41
  • A6=41
  • AMUX=15
  • AQ=66
  • AX=52
  • B=18
  • B1=5
  • B2=12
  • B3=22
  • B4=27
  • B5=29
  • B6=28
  • BMUX=11
  • BQ=38
  • BX=28
  • C=18
  • C1=4
  • C2=11
  • C3=16
  • C4=21
  • C5=26
  • C6=25
  • CE=18
  • CLK=87
  • CMUX=10
  • CQ=29
  • CX=21
  • D=20
  • D1=8
  • D2=10
  • D3=22
  • D4=24
  • D5=27
  • D6=27
  • DMUX=10
  • DQ=39
  • DX=30
  • SR=58
 
Tool Usage
Command Line History
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-2 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-2 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-2 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-2 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-2 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-2 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 7 5 0 0 0 0 0
bitgen 31 31 0 0 0 0 0
cse_server 3 3 0 0 0 0 0
map 35 32 0 0 0 0 0
ngcbuild 13 13 0 0 0 0 0
ngdbuild 37 37 0 0 0 0 0
par 32 32 0 0 0 0 0
trce 32 32 0 0 0 0 0
xst 110 110 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=true PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2018-05-28T11:02:53
PROP_intWbtProjectID=B998B51339B749A49736A6F4F9775C0E PROP_intWbtProjectIteration=5
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_xilxBitgStart_Clk=JTAG Clock
PROP_xilxBitgStart_IntDone=true PROP_AutoTop=true
PROP_DevFamily=Spartan6 PROP_xilxBitgCfg_GenOpt_BinaryFile=true
PROP_DevDevice=xc6slx16 PROP_DevFamilyPMName=spartan6
PROP_DevPackage=csg324 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-2 PROP_PreferredLanguage=VHDL
FILE_CDC=1 FILE_COREGEN=1
FILE_UCF=1 FILE_VHDL=11
 
Core Statistics
Core Type=blk_mem_gen_v7_3
c_addra_width=13 c_addrb_width=13 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=9 c_common_clk=0
c_default_data=0 c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=masked_value
c_enable_32bit_address=0 c_family=spartan6 c_has_axi_id=0 c_has_ena=0
c_has_enb=0 c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0
c_has_mux_output_regs_a=0 c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0
c_has_rsta=0 c_has_rstb=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0
c_init_file=BlankString c_init_file_name=no_coe_file_loaded c_inita_val=0 c_initb_val=0
c_interface_type=0 c_load_init_file=0 c_mem_type=0 c_mux_pipeline_stages=0
c_prim_type=1 c_read_depth_a=8192 c_read_depth_b=8192 c_read_width_a=8
c_read_width_b=8 c_rst_priority_a=CE c_rst_priority_b=CE c_rst_type=SYNC
c_rstram_a=0 c_rstram_b=0 c_sim_collision_check=ALL c_use_bram_block=0
c_use_byte_wea=0 c_use_byte_web=0 c_use_default_data=0 c_use_ecc=0
c_use_softecc=0 c_wea_width=1 c_web_width=1 c_write_depth_a=8192
c_write_depth_b=8192 c_write_mode_a=WRITE_FIRST c_write_mode_b=WRITE_FIRST c_write_width_a=8
c_write_width_b=8 c_xdevicefamily=spartan6
Core Type=chipscope_icon_v1_06_a
c_build_revision=0 c_constraint_type=embedded c_core_major_ver=1 c_core_minor_alpha_ver=97
c_core_minor_ver=2 c_core_type=1 c_example_design=false c_major_version=14
c_mfg_id=1 c_minor_version=7 c_num_control_ports=1 c_part_idcode_register=0
c_use_bufr=0 c_use_control0=1 c_use_control1=0 c_use_control10=0
c_use_control11=0 c_use_control12=0 c_use_control13=0 c_use_control14=0
c_use_control2=0 c_use_control3=0 c_use_control4=0 c_use_control5=0
c_use_control6=0 c_use_control7=0 c_use_control8=0 c_use_control9=0
c_use_ext_bscan=0 c_use_jtag_bufg=1 c_use_new_parser=0 c_use_sim=0
c_use_softbscan=0 c_use_unused_bscan=0 c_use_xst_tck_workaround=1 c_user_scan_chain=1
c_xco_list=Number_Control_Ports=1;Use_Ext_Bscan=false;User_Scan_Chain=USER1;Enable_Jtag_Bufg=true;Use_Unused_Bscan=false;Use_Softbscan=false c_xdevicefamily=spartan6
Core Type=chipscope_ila_v1_05_a
c_build_revision=0 c_constraint_type=embedded c_core_major_ver=1 c_core_minor_alpha_ver=97
c_core_minor_ver=4 c_core_type=2 c_data_depth=1024 c_data_width=1
c_example_design=false c_ext_cap_pin_mode=0 c_ext_cap_rate_mode=0 c_ext_cap_use_reg=1
c_m0_tpid=0 c_m0_type=1 c_m10_tpid=10 c_m10_type=0
c_m11_tpid=11 c_m11_type=0 c_m12_tpid=12 c_m12_type=0
c_m13_tpid=13 c_m13_type=0 c_m14_tpid=14 c_m14_type=0
c_m15_tpid=15 c_m15_type=0 c_m1_tpid=1 c_m1_type=0
c_m2_tpid=2 c_m2_type=0 c_m3_tpid=3 c_m3_type=0
c_m4_tpid=4 c_m4_type=0 c_m5_tpid=5 c_m5_type=0
c_m6_tpid=6 c_m6_type=0 c_m7_tpid=7 c_m7_type=0
c_m8_tpid=8 c_m8_type=0 c_m9_tpid=9 c_m9_type=0
c_major_version=14 c_mcnt0_width=1 c_mcnt10_width=1 c_mcnt11_width=1
c_mcnt12_width=1 c_mcnt13_width=1 c_mcnt14_width=1 c_mcnt15_width=1
c_mcnt1_width=1 c_mcnt2_width=1 c_mcnt3_width=1 c_mcnt4_width=1
c_mcnt5_width=1 c_mcnt6_width=1 c_mcnt7_width=1 c_mcnt8_width=1
c_mcnt9_width=1 c_mfg_id=1 c_minor_version=7 c_num_ext_cap_pins=8
c_num_match_units=1 c_num_tseq_cnt=0 c_num_tseq_states=16 c_ram_type=1
c_srl16_type=2 c_tc_mcnt_width=1 c_timestamp_depth=512 c_timestamp_type=0
c_timestamp_width=32 c_trig0_width=2 c_trig10_width=1 c_trig11_width=1
c_trig12_width=1 c_trig13_width=1 c_trig14_width=1 c_trig15_width=1
c_trig1_width=1 c_trig2_width=1 c_trig3_width=1 c_trig4_width=1
c_trig5_width=1 c_trig6_width=1 c_trig7_width=1 c_trig8_width=1
c_trig9_width=1 c_tseq_cnt0_width=1 c_tseq_cnt1_width=1 c_tseq_type=1
c_use_atc_clkin=0 c_use_data=0 c_use_gap=0 c_use_inv_clk=0
c_use_mcnt0=0 c_use_mcnt1=0 c_use_mcnt10=0 c_use_mcnt11=0
c_use_mcnt12=0 c_use_mcnt13=0 c_use_mcnt14=0 c_use_mcnt15=0
c_use_mcnt2=0 c_use_mcnt3=0 c_use_mcnt4=0 c_use_mcnt5=0
c_use_mcnt6=0 c_use_mcnt7=0 c_use_mcnt8=0 c_use_mcnt9=0
c_use_rpm=1 c_use_storage_qual=1 c_use_tc_mcnt=0 c_use_trig0=1
c_use_trig1=0 c_use_trig10=0 c_use_trig11=0 c_use_trig12=0
c_use_trig13=0 c_use_trig14=0 c_use_trig15=0 c_use_trig2=0
c_use_trig3=0 c_use_trig4=0 c_use_trig5=0 c_use_trig6=0
c_use_trig7=0 c_use_trig8=0 c_use_trig9=0 c_use_trig_out=0
c_use_trigdata0=1 c_use_trigdata1=0 c_use_trigdata10=0 c_use_trigdata11=0
c_use_trigdata12=0 c_use_trigdata13=0 c_use_trigdata14=0 c_use_trigdata15=0
c_use_trigdata2=0 c_use_trigdata3=0 c_use_trigdata4=0 c_use_trigdata5=0
c_use_trigdata6=0 c_use_trigdata7=0 c_use_trigdata8=0 c_use_trigdata9=0
c_xco_list=Component_Name=ila_pro_0;Number_Of_Trigger_Ports=1;Max_Sequence_Levels=16;Use_RPMs=true;Enable_Trigger_Output_Port=false;Sample_On=Rising;Sample_Data_Depth=1024;Enable_Storage_Qualification=true;Data_Same_As_Trigger=true;Data_Port_Width=0;Trigger_Port_Width_1=2;Match_Units_1=1;Counter_Width_1=Disabled;Match_Type_1=basic_with_edges;Exclude_From_Data_Storage_1=false;Trigger_Port_Width_2=1;Match_Units_2=1;Counter_Width_2=Disabled;Match_Type_2=basic;Exclude_From_Data_Storage_2=false;Trigger_Port_Width_3=1;Match_Units_3=1;Counter_Width_3=Disabled;Match_Type_3=basic;Exclude_From_Data_Storage_3=false;Trigger_Port_Width_4=1;Match_Units_4=1;Counter_Width_4=Disabled;Match_Type_4=basic;Exclude_From_Data_Storage_4=false;Trigger_Port_Width_5=1;Match_Units_5=1;Counter_Width_5=Disabled;Match_Type_5=basic;Exclude_From_Data_Storage_5=false;Trigger_Port_Width_6=1;Match_Units_6=1;Counter_Width_6=Disabled;Match_Type_6=basic;Exclude_From_Data_Storage_6=false;Trigger_Port_Width_7=1;Match_Units_7=1;Counter_Width_7=Disabled;Match_Type_7=basic;Exclude_From_Data_Storage_7=false;Trigger_Port_Width_8=1;Match_Units_8=1;Counter_Width_8=Disabled;Match_Type_8=basic;Exclude_From_Data_Storage_8=false;Trigger_Port_Width_9=1;Match_Units_9=1;Counter_Width_9=Disabled;Match_Type_9=basic;Exclude_From_Data_Storage_9=false;Trigger_Port_Width_10=1;Match_Units_10=1;Counter_Width_10=Disabled;Match_Type_10=basic;Exclude_From_Data_Storage_10=false;Trigger_Port_Width_11=1;Match_Units_11=1;Counter_Width_11=Disabled;Match_Type_11=basic;Exclude_From_Data_Storage_11=false;Trigger_Port_Width_12=1;Match_Units_12=1;Counter_Width_12=Disabled;Match_Type_12=basic;Exclude_From_Data_Storage_12=false;Trigger_Port_Width_13=1;Match_Units_13=1;Counter_Width_13=Disabled;Match_Type_13=basic;Exclude_From_Data_Storage_13=false;Trigger_Port_Width_14=1;Match_Units_14=1;Counter_Width_14=Disabled;Match_Type_14=basic;Exclude_From_Data_Storage_14=false;Trigger_Port_Width_15=1;Match_Units_15=1;Counter_Width_15=Disabled;Match_Type_15=basic;Exclude_From_Data_Storage_15=false;Trigger_Port_Width_16=1;Match_Units_16=1;Counter_Width_16=Disabled;Match_Type_16=basic;Exclude_From_Data_Storage_16=false c_xdevicefamily=spartan6
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BSCAN_SPARTAN6=1 NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=75
NGDBUILD_NUM_FDC=9 NGDBUILD_NUM_FDCE=16 NGDBUILD_NUM_FDE=35 NGDBUILD_NUM_FDP=6
NGDBUILD_NUM_FDR=78 NGDBUILD_NUM_FDRE=66 NGDBUILD_NUM_FDS=10 NGDBUILD_NUM_GND=9
NGDBUILD_NUM_IBUF=1 NGDBUILD_NUM_INV=8 NGDBUILD_NUM_LDC=1 NGDBUILD_NUM_LUT1=74
NGDBUILD_NUM_LUT2=31 NGDBUILD_NUM_LUT3=64 NGDBUILD_NUM_LUT4=97 NGDBUILD_NUM_LUT5=14
NGDBUILD_NUM_LUT6=28 NGDBUILD_NUM_MUXCY=33 NGDBUILD_NUM_MUXCY_L=62 NGDBUILD_NUM_MUXF7=12
NGDBUILD_NUM_MUXF8=2 NGDBUILD_NUM_OBUF=10 NGDBUILD_NUM_RAMB16BWER=8 NGDBUILD_NUM_RAMB8BWER=1
NGDBUILD_NUM_SRL16=2 NGDBUILD_NUM_SRL16E=1 NGDBUILD_NUM_SRLC16E=27 NGDBUILD_NUM_SRLC32E=29
NGDBUILD_NUM_VCC=12 NGDBUILD_NUM_XORCY=83
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BSCAN_SPARTAN6=1 NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_FD=75 NGDBUILD_NUM_FDC=9
NGDBUILD_NUM_FDCE=16 NGDBUILD_NUM_FDE=35 NGDBUILD_NUM_FDP=6 NGDBUILD_NUM_FDR=78
NGDBUILD_NUM_FDRE=66 NGDBUILD_NUM_FDS=10 NGDBUILD_NUM_GND=9 NGDBUILD_NUM_IBUF=1
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=8 NGDBUILD_NUM_LDC=1 NGDBUILD_NUM_LUT1=74
NGDBUILD_NUM_LUT2=31 NGDBUILD_NUM_LUT3=64 NGDBUILD_NUM_LUT4=97 NGDBUILD_NUM_LUT5=14
NGDBUILD_NUM_LUT6=28 NGDBUILD_NUM_MUXCY=33 NGDBUILD_NUM_MUXCY_L=62 NGDBUILD_NUM_MUXF7=12
NGDBUILD_NUM_MUXF8=2 NGDBUILD_NUM_OBUF=10 NGDBUILD_NUM_RAMB16BWER=8 NGDBUILD_NUM_RAMB8BWER=1
NGDBUILD_NUM_SRL16E=3 NGDBUILD_NUM_SRLC16E=27 NGDBUILD_NUM_SRLC32E=29 NGDBUILD_NUM_TS_TIMESPEC=1
NGDBUILD_NUM_VCC=12 NGDBUILD_NUM_XORCY=83
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx16-2-csg324
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -sd=<No customer specific name> -write_timing_constraints=NO
-cross_clock_analysis=NO -bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100
-dsp_utilization_ratio=100 -reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto
-safe_implementation=No -fsm_style=LUT -ram_extract=Yes -ram_style=Auto
-rom_extract=Yes -shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO
-resource_sharing=YES -async_to_sync=NO -use_dsp48=Auto -iobuf=YES
-max_fanout=100000 -bufg=16 -register_duplication=YES -register_balancing=No
-optimize_primitives=NO -use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto
-iob=Auto -equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5